Výsledky vyhledávání - "Kornelis A. Vissers"

Autor: Paul Lieverse, Kornelis A. Vissers, P. van der Wolf, Ed F. Deprettere

Publikováno v: The Journal of VLSI Signal Processing. 29:197-207

We present a methodology for the exploration of signal processing architectures at the system level. The methodology, named SPADE, provides a means to quickly build models of architectures at an abstract level, to easily map applications, modeled as

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::77e1cb1edff3585c9fe7728e81605dd5
https://doi.org/10.1023/a:1012231429554

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TriMedia CPU64 architecture

Autor: Harald Vranken, M.I.A. Tromp, Kornelis A. Vissers, J.T.J. van Eijndhoven, P. van der Wolf, F.W. Sijstermans, P. Struik, Evert-Jan D. Pol, Andy D. Pimentel, Rudolf Henricus Johannes Bloks

Publikováno v: ICCD

We present a new VLIW core as a successor to the TriMedia TM1000. The processor is targeted for embedded use in media-processing devices like DTVs and set-top boxes. Intended as a core, its design must be supplemented with on-chip co-processors to ob

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c7b35594ed2db826ec31c57a28ffc217
https://doi.org/10.1109/iccd.1999.808601

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MPEG-compliant entropy decoding on FPGA-augmented TriMedia/CPU64

Autor: M. Simat, Stamatis Vassiliadis, Sorin Cotofana, Kornelis A. Vissers, J.T.J. van Eijndhoven

Publikováno v: Delft University of Technology
FCCM

The paper presents a Design Space Exploration (DSE) experiment which has been carried out in order to determine the optimum FPGA-based Variable-Length Decoder (VLD) computing resource and its associated instructions, with respect to an entropy decodi

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9ba19bd718f9d0cb20b2ac2a5fbb966e
https://research.tudelft.nl/en/publications/f097b116-756f-47f5-a54c-8252371ae1f2

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MPEG macroblock parsing and Pel reconstruction on an FPGA-augmented TriMedia processor

Autor: Kornelis A. Vissers, Mihai Sima, Sorin Cotofana, S. Vasseliadis, J.T.J. van Eijndhoven

Publikováno v: Delft University of Technology
ICCD

This paper describes an experiment which aims to reveal the potential impact on performance yielded by augmenting a TriMedia-CPU64 processor with a multiple-context FPGA core. We first propose an extension of the TriMedia CPU64 architecture, which co

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::99355b90243ce0f98bdfe5a71c96cc9c
https://research.tudelft.nl/en/publications/a5404bbe-7b4f-4cbc-98bb-0ffd28d8e9f2

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