Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Konstantinos Aisopos"'
Publikováno v:
ICCD
Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. Aiming towards seamless NoC operation in the presence of faulty c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5dd79b0be42f85b39abd9362906e3959
https://doi.org/10.1109/iccd.2014.6974715
https://doi.org/10.1109/iccd.2014.6974715
Publikováno v:
NOCS
Networks-on-Chips (NoCs) are experiencing escalating susceptibility to wear-out and reduced reliability, with the risk of becoming the key point of failure in an entire multicore chip. In this paper we propose Hermes, a highly-robust, distributed fau
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fdbe21699037785212d1b98e18ae9028
https://doi.org/10.1109/nocs.2014.7008782
https://doi.org/10.1109/nocs.2014.7008782
Autor:
Konstantinos Aisopos, Li-Shiuan Peh
Publikováno v:
MICRO
Aggressive transistor scaling continues to increase integration capacity with each new technology node, but technology downscaling also increases the vulnerability of semiconductor devices and causes silicon failures. Thus, fault-tolerant architectur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a3952d1c46c7ecad7e1ce18d3397432
https://doi.org/10.1145/2155620.2155627
https://doi.org/10.1145/2155620.2155627
Publikováno v:
DAC
MIT web domain
MIT web domain
Process Variation (PV) is increasingly threatening the reliability of Networks-on-Chips. Thus, various resilient router designs have been recently proposed and evaluated. However, these evaluations assume random fault distributions, which result in 5
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4678e391a45383e7d209c8310bd6512a
https://doi.org/10.1145/2024724.2024931
https://doi.org/10.1145/2024724.2024931
Publikováno v:
IPDPS
Many data centers employ server consolidation to maximize the efficiency of platform resource usage. As a result, multiple virtual machines (VMs) simultaneously run on each data center platform. Contention for shared resources between these virtual m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7bd00e26b29fa8175e94351b021c8ae8
https://doi.org/10.1109/ipdps.2011.98
https://doi.org/10.1109/ipdps.2011.98
Autor:
Konstantinos Aisopos, Jaideep Moses, Ramesh Illikkal, Donald Newell, Srihari Makineni, Ravi Iyer, Aamer Jaleel
Publikováno v:
ISPASS
CMPs have now become mainstream and are growing in complexity with more cores, several shared resources (cache, memory, etc) and the potential for additional heterogeneous elements. In order to manage these resources, it is becoming critical to optim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cc3cb315673da9ef671633238d7e66c0
https://doi.org/10.1109/ispass.2009.4919643
https://doi.org/10.1109/ispass.2009.4919643
Publikováno v:
CODES+ISSS
Open Core Protocol (OCP) is a standard on-chip core interface specification. The current release is flexible and configurable to support the communication needs of a wide range of Intellectual Property cores, and is now in widespread use. However, it
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5d2d338100e9766c7ca7c93a0a92d484
https://doi.org/10.1145/1450135.1450173
https://doi.org/10.1145/1450135.1450173
Autor:
Athanasios Kakarountas, Fotis Aisopos, Konstantinos Aisopos, H. E. Michail, Dimitrios Schinianakis
Publikováno v:
MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference.
A design approach to create small-sized high-speed implementation of the new version of secure hash algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed imple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa9547d48a3239dcff47408d5fa1c9e0
https://doi.org/10.1109/melcon.2006.1653036
https://doi.org/10.1109/melcon.2006.1653036
Publikováno v:
IEEE Workshop on Signal Processing Systems Design and Implementation, 2005..
A design approach to create small-sized high-speed implementation of the new version of secure hash algorithm is proposed. The resulted design can be easily embedded to operate in HMAC IP cores, providing a high degree of security. The proposed imple
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b1660405299abec74251166d5ec886ac
https://doi.org/10.1109/sips.2005.1579846
https://doi.org/10.1109/sips.2005.1579846
Publikováno v:
Architecture of Computing Systems-ARCS 2006 ISBN: 9783540327653
ARCS
ARCS
Data cache compression is actively studied as a venue to make bet ter use of on-chip transistors, increase apparent capacity of caches, and hide the long memory latencies. While several techniques have been proposed for L2 compression, L1 compression
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90dd44aef813b55f9a25e1f305c52ca4
https://doi.org/10.1007/11682127_9
https://doi.org/10.1007/11682127_9
