Zobrazeno 1 - 7
of 7
pro vyhledávání: '"Konstantin Korablev"'
Autor:
Shesh Mani Pandey, Konstantin Korablev, Peter Zeitzoff, Sudarshan Narayanan, Amaury Gendron-Hansen, Edmund Banghart, Francis Benistant
Publikováno v:
Solid-State Electronics. 123:44-50
A novel TCAD conductance integration method is presented to evaluate and extract the channel resistance as well as the three-dimensional (3D) parasitic resistance components in a FinFET device. It is shown that results with this method agree well wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::32744fe2e64d527e0ca76e226185e840
https://doi.org/10.1016/j.sse.2016.05.018
https://doi.org/10.1016/j.sse.2016.05.018
Autor:
Amaury Gendron-Hansen, Konstantin Korablev, Francis Benistant, Jin Cho, James Egley, Ivan Chakarov
Publikováno v:
2015 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
In this paper, we analyze the mechanical stress induced from source/drain embedded SiGe (eSiGe) in multiple generations of FinFET technologies. By leveraging TCAD simulations, we show that high stress over the entire fin height could be achieved with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::620fe3f41e69a211141c98fdcb798d61
https://doi.org/10.1109/sispad.2015.7292349
https://doi.org/10.1109/sispad.2015.7292349
Autor:
Jagar Singh, Konstantin Korablev, Jian-Hsing Lee, Mahadeva Iyer Natarajan, Manjunatha Prabhu, Shesh Mani Pandey
Publikováno v:
IRPS
Method for making Finfet ESD performance comparable to bulk planar ESD devices is demonstrated using a simple but effective process. Low FIN silicon volume compared to their counterparts in bulk planar process is compensated with the additional deep
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3333fdc11cb66f6ce15addbe0334d6c
https://doi.org/10.1109/irps.2015.7112721
https://doi.org/10.1109/irps.2015.7112721
Autor:
L. Jiang, El Mehdi Bazizi, J. P. Goh, Francis Benistant, Tom Herrmann, H. van Meer, J. H. M. Tin, Konstantin Korablev, Alban Zaka, Manoj Joshi
Publikováno v:
ESSDERC
Predictive TCAD tool is crucial for several reasons such as to provide pre-silicon data, shorten the technology development cycle and reduce the fabrication cost. In this paper, advanced 3D TCAD process and device simulations is used to gain physical
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90516845f152afec105554051996a282
https://doi.org/10.1109/essderc.2014.6948830
https://doi.org/10.1109/essderc.2014.6948830
Autor:
J. H. M. Tin, Alban Zaka, Tom Herrmann, H. van Meer, El Mehdi Bazizi, Francis Benistant, Konstantin Korablev, Manoj Joshi, L. Jiang, J. P. Goh
Publikováno v:
2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
The impacts of FinFET channel and extension S/D region implantations on relevant device parameters such as electrostatic control and Vth mismatch (MM) are investigated. We used 3D TCAD process and device simulations to gain physical understanding and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b067822d636082f713b0484cf6a009bd
https://doi.org/10.1109/sispad.2014.6931554
https://doi.org/10.1109/sispad.2014.6931554
Autor:
Edmund Banghart, B. Liu, Y. Liu, M.H. Chi, Geetha S. Aluri, Manfred Eller, M. H. Nam, Suresh Uppal, Anurag Mittal, P. Paliwoda, Konstantin Korablev, Srikanth Samavedam
Publikováno v:
2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
A novel anti-fuse memory array is presented in this paper featuring one-capacitor (1C) per bit-cell design and fully compatible with 14nm FinFET CMOS technology. The rectifying I-V characteristics of the metal-insulator-semiconductor (MIS) structure
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1896ce080847d668491fa2ab51bbec3d
https://doi.org/10.1109/vlsit.2014.6894356
https://doi.org/10.1109/vlsit.2014.6894356
Autor:
A. Keshavarzi, James Egley, M-R. Lin, Jin Cho, Konstantin Korablev, Subramani Kengeri, Andreas Knorr, R. J. Miller, S. Luning, Shibly S. Ahmed, U. Schroeder, Andy Wei, Rod Augur, C-H. Shaw, Srinivasa Banna, G. S. Bartlett, Kingsuk Maitra, Dinesh Somasekhar, A. Halliyal, Suresh Venkatesan, Mahbub Rashed
Publikováno v:
2011 International Electron Devices Meeting.
Industry's extensive knowledge of fabricating bulk CMOS planar transistors has made them the device of choice for the cost sensitive foundry semiconductor sector. On advanced nodes the scaling benefits for SoCs will be based on a set of Key Performan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86911f759ffd1df1791dc1c1b01477c8
https://doi.org/10.1109/iedm.2011.6131485
https://doi.org/10.1109/iedm.2011.6131485