Zobrazeno 1 - 10
of 24
pro vyhledávání: '"Koji Shibutani"'
Autor:
Yuuki Uchida, Yasumasa Tsukamoto, Koji Shibutani, Kazutoshi Kobayashi, Yoshio Takazawa, Mitsuhiko Igarashi, Makoto Yabuuchi
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1536-1545
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::06e79a94c7315a6c5d0cb4819c11ac77
https://doi.org/10.1587/transfun.2020kep0017
https://doi.org/10.1587/transfun.2020kep0017
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 19:97-103
This paper discusses the design methodology of a voltage and temperature-sensitive ring oscillator (VT_RO), whose frequency has a similar dependence on voltages and temperatures as that of worn-out stress strength of a gate time-dependent dielectric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::adc6b86fdf2c7d446103e165089329d7
https://doi.org/10.1109/tdmr.2018.2886566
https://doi.org/10.1109/tdmr.2018.2886566
Publikováno v:
IET Circuits, Devices & Systems. 12:182-188
The authors propose an on-chip wear-out monitoring technique, which is based on monitoring the environmental conditions experienced by a digital circuit. The frequency of the T-sensitive ring oscillator (RO) emulates the wear-out stress strength caus
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0736b5649f489b165360e78349e16d50
https://doi.org/10.1049/iet-cds.2017.0153
https://doi.org/10.1049/iet-cds.2017.0153
Autor:
Koji Shibutani, Yoshio Takazawa, Mitsuhiko Igarashi, Yuuki Uchida, Yasumasa Tsukamoto, Makoto Yabuuchi
Publikováno v:
IRPS
This paper presents an analysis of impact of local bias temperature instability (BTI) by measuring Ring-Oscillators (RO) with short stage and its impact on Logic circuit and SRAM. The evaluation result of local BTI variation based on measuring RO at
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::272c0d9011290b4893d8f18c1dfc6e8a
https://doi.org/10.1109/irps.2019.8720508
https://doi.org/10.1109/irps.2019.8720508
Autor:
Daisuke Oshida, Koji Shibutani, Ota Naoya, Konishi Shinya, Kan Takeuchi, Tomohiro Iwashita, Tetsuya Kokubun, Fumio Tsuchiya, Masaki Shimada, Takashi Yasumasu
Publikováno v:
IRPS
The on-chip stress monitor was experimentally implemented in a 28 nm automotive micro-controller-unit (MCU) to demonstrate the contribution to long-term fatigue monitoring of the MCU as well as short-term anomaly finding of the system. The monitor co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f29fdfe46a2c4b228a62ebe49ee7823
https://doi.org/10.1109/irps.2019.8720583
https://doi.org/10.1109/irps.2019.8720583
Autor:
Yasumasa Tsukamoto, Koji Shibutani, Koji Nii, Mitsuhiko Igarashi, Yuuki Uchida, Yoshio Takazawa
Publikováno v:
IRPS
This paper presents an analysis methodology of the impact of Local Layout Effect (LLE) of bias temperature instability (BTI) on logic circuits by measuring Ring-Oscillators (RO) consist of many kinds of standard cells and shows its measurement result
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6848e7b47a46d2fe98682d7189320ba2
https://doi.org/10.1109/irps.2018.8353654
https://doi.org/10.1109/irps.2018.8353654
Publikováno v:
A-SSCC
We propose an on-chip bias temperature instabilities (BTI) monitor by using standard cell based unbalanced ring-oscillator (RO). The monitor consists of NAND and NOR with extremely large difference in drive strength, which enables 4.2x sensitivity to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8ba664d1db99c23167810aeca80f2995
https://doi.org/10.1109/asscc.2017.8240251
https://doi.org/10.1109/asscc.2017.8240251
Publikováno v:
ESSCIRC
We propose wear-out estimator of remaining lifetime, which consists of two types of custom ring oscillators (ROs) and cumulative stress counters only. This on-chip estimator operates independently without disruption of MCU main operations and is aime
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::825629a253b851e6951fc74b20e795aa
https://doi.org/10.1109/esscirc.2016.7598293
https://doi.org/10.1109/esscirc.2016.7598293
Autor:
Yasumasa Tsukamoto, Kazunori Onozawa, Hiroaki Matsushita, Takeshi Okagaki, H. Ojiro, Masao Morimoto, Koji Shibutani, Koji Nii
Publikováno v:
Proceedings of the 2015 International Conference on Microelectronic Test Structures.
An area effective delay cell can be achieved in FinFET device with effective utilization of its parasitic capacitance, even though it is considered as disadvantage. We confirmed that parasitic capacitance of local interconnect can be a benefit for a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::46290d8cdfd4a8d865671024ddeaec7d
https://doi.org/10.1109/icmts.2015.7106125
https://doi.org/10.1109/icmts.2015.7106125