Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Koji Hosono"'
Autor:
Yasuyuki Kajitani, Kazushige Kanda, Manabu Sato, Takahiro Shimizu, Hiroshi Sugawara, Junji Musha, Yee Lih Koh, Tomoki Nakagawa, Kazuaki Kawaguchi, Takahiro Sugimoto, Koji Hosono, Jumpei Sato, Mario Sako, Yusuke Ochi, Tomoaki Nakano, Katsuaki Sakurai, Ryo Fukuda, Ryoichi Tachibana, Naoki Kobayashi, Juan Lee, Hiroki Date, Hiroaki Nasu, Koichi Kawakami, Makoto Miakashi, Dai Nakamura, Yuuki Matsumoto, Jieyun Zhou, Shuo Chen, Tadashi Someya, Hiroshi Nakamura, Kosuke Yanagidaira, Namasivayam Raghunathan, Takeshi Ogawa, M. Kojima, Masami Masuda, Toshifumi Hashimoto, Jun Nakai, Takahisa Kawabe, Taira Shibuya, Masatsugu Ogawa, Osamu Nagao, Takahiro Yamashita, Teruo Takagiwa, Toshiki Hisada, Tomoharu Hashiguchi, Yasushi Nagadomi, Mizuki Uda, Noboru Shibata, Takatoshi Minamoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:178-188
A 1.33-Tb 4-bit/cell quadruple-level (QLC) 3-D flash memory in a 96-word-line (WL)-layer technology that achieves 8.5 Gb/mm2 has been developed. This is the biggest capacity and the highest bit density ever reported. A source-bias-negative-sense with
Autor:
Siddhesh Darne, Teruo Takagiwa, Junya Matsuno, Yuki Shimizu, Naoya Tokiwa, Kei Shiraishi, Tetsuaki Utsumi, Hiroyuki Mizukoshi, Koji Hosono, Masatsugu Kojima, Junji Musha, Takuyo Kodama, Osamu Kobayashi, Masahiro Kano, Takeshi Hioka, Naoki Ookuma, Yuki Kuniyoshi, Takahiro Sugimoto, Ryoichi Tachibana, Hiroshi Sugawara, Hiroki Date, Kazuhide Yoneya, Srinivas Rajendra, Akira Arimizu, Yoshito Katano, Mitsuhiro Abe, Keiji Tsunoda, Masakazu Ehama, Toshifumi Hashimoto, Tianyu Tang, Tomofumi Fujimura, Ryo Fukuda, Jason Li, Hiroshi Maejima, Shintaro Hayashi, Akio Sugahara, Kei Akiyama, Koji Kato, Toru Miwa, Kensuke Yamamoto, Masahiro Yoshihara, Katsuaki Sakurai, Itaru Yamaguchi, Tsutomu Higuchi, Mizuki Kaneko, Jumpei Sato, Kazumasa Yamamoto, Yasuhiro Suematsu, Mitsuyuki Watanabe, Ryuji Yamashita, Venky Ramachandra, Kosuke Yanagidaira, Jiwang Lee, Kazuko Inuzuka, Hirotoshi Mori, Takatoshi Minamoto, Tomoharu Hashiguchi, Mitsuaki Honma, Juan Lee
Publikováno v:
ISSCC
This work demonstrates a novel 1Tb 3D Flash memory chip that has an area efficiency of 10.4Gb/mm2 in a 3b/cell technology. Using a circuit under array (CUA) design technique and over 170 word-line (WL) layers, the chip achieves 33% higher bit density
Autor:
J. Zhou, Teruo Takagiwa, Toshifumi Hashimoto, Y. Ochi, Toshiki Hisada, Mario Sako, Takahiro Yamashita, M. Uda, Takatoshi Minamoto, Hiroshi Sugawara, T. Kawabe, Noboru Shibata, N. Raghunathan, Junichi Sato, Koji Hosono, Osamu Nagao, T. Ogawa, Naoki Kobayashi, T. Someya, Shuo Chen, Ryo Fukuda, Koichi Kawakami, H. Date, Makoto Miakashi, Y. Matsumoto, Takahiro Shimizu, M. Sato, J. Nakai, Naohito Morozumi, M. Ogawa, Tomoharu Hashiguchi, Tomohiro Sugimoto, H. Takamoto, T. Nakano, T. Nakagawa, Masami Masuda, T. Shibuya, M. Kojima, Hiroshi Nakamura, H. Nasu, Kosuke Yanagidaira, Kiyofumi Sakurai, Yasushi Nagadomi, Kazuaki Kawaguchi, Yasuyuki Kajitani, Kazushige Kanda, Junji Musha, Ryoichi Tachibana, T. Kaneko, Y. L. Koh, Juan Lee, Dai Nakamura
Publikováno v:
ISSCC
Since 3D-Flash memory took over for 2D-Flash memory, chip capacity has continuously improved [1]–[3]. In the 2D-Flash era, 2b/cell (MLC) offered higher performance and reliability, while a 3b/cell (TLC) offered the lowest cost. Thanks to a larger f
Autor:
Katsuaki Sakurai, Feng Lu, Kenro Kubota, Hiroshi Sugawara, Yoshihiko Shindo, Steve Choi, Junji Musha, Yusuke Ochi, Hao Nguyen, Hiroshi Nakamura, Yee Koh, Yasuhiro Suematsu, Ryo Fukuda, Tomoko Nishiuchi, Spiros Georgakis, Keyur Payak, Masatsugu Kojima, Sanad Bushnaq, Naoki Kobayashi, Kwang-ho Kim, Hiroe Minagawa, Manabu Sato, Yuuki Shimizu, Naoaki Kanagawa, Susumu Fujimura, Teruo Takagiwa, Kenichi Abe, Takahiro Shimizu, Toshiki Hisada, Taichi Wakui, Hiroshi Maejima, Susumu Ozawa, Makoto Miakashi, Srinivas Rajendra, Kazushige Kanda, Hiroshi Yoshihara, Namas Raghunathan, Akihiro Imamoto, Koji Hosono, Dong He, Satoshi Inoue, Masatsugu Ogawa, Seungpil Lee, Jumpei Sato, Fumihiro Kono, Yuui Shimizu, Kazuhiko Satou, Takuya Futatsuyama, Venky Ramachandra, Naohito Morozumi, Weihan Wang, Tomoharu Hashiguchi, Hicham Haibi, Noboru Shibata, Takatoshi Minamoto, Xu Li, Kouichirou Yamaguchi, Toshifumi Hashimoto, Takahiro Yamashita, Ken Cheah, Mitsuhiro Abe, Tetsuya Kaneko, Tadashi Yasufuku, Takahiro Sugimoto
Publikováno v:
ISSCC
The first multi-layer stacked 3D Flash memory was proposed as BiCS FLASH in 2007 [1]. Since then, memory bit density has grown rapidly due to the increase in the number of stacked layers from continuous 3D technology innovations. On the other hand, t
Publikováno v:
Proceedings of International Conference on Leading Edge Manufacturing in 21st century : LEM21. :381-384
Publikováno v:
Key Engineering Materials. :919-924
A three-axis mosaic surface encoder, which can measure the X-directional position and the Y-, Z-directional straightness of the linear stage in a long range, is proposed. The three-axis mosaic surface encoder is composed of multiple scanning probes a
Publikováno v:
Precision Engineering. 36:576-585
A three-axis surface encoder was developed for stage motion measurement with sub-nanometric resolutions. The surface encoder was composed of a scale XY planar grating with X- and Y-directional periodic grating structures and an optical sensor head fo
Publikováno v:
International Journal of Automation Technology. 5:91-96
The surface encoder we propose for simultaneously measuring XYZ-directional displacements consists of a XY-axis with a scale grating and an optical sensor head. The XY-axis scale grating size determines the surface encoder’s measurement range in pl
Autor:
Koji Hosono, M. Kojima, Shigeo Ohshima, Susumu Fujimura, Shouchang Tsao, N. Hayashida, H. Waki, Ken Oowada, Jeffrey W. Lutze, Makoto Iwai, G. Hemink, Kiyofumi Sakurai, H. Otake, Sumio Tanaka, Mehrdad Mofidi, Shih-Chung Lee, Y. Nozawa, Yohji Watanabe, Y. Kameda, Ken Takeuchi, Jun Wan, Masanobu Shirakawa, K. Hatakeyama, A. Cernea, Teruhiko Kamei, Yoshihiko Shindo, Hitoshi Shiga, Yan Li, Takuya Futatsuyama, Jia-Yi Fu, Masaaki Higashitani, Masayuki Ichige, K. Kanazawa, Naoya Tokiwa, Shinji Sato
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:219-232
A single 3.3-V only, 8-Gb NAND flash memory with the smallest chip to date, 98.8 mm2, has been successfully developed. This is the world's first integrated semiconductor chip fabricated with 56-nm CMOS technologies. The effective cell size including
Autor:
Koji Hosono, Mitsufumi Naoe, Toru Miyauchi, Masaaki Miyajima, Kanji Takeuchi, Hiroyuki Matsumoto
Publikováno v:
Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII.
Precision control of critical dimensions (CD) in modern photomask manufacturing is conventionally accomplished by measuring of CD check patterns allocated inside photomask area. Recently, due to use of immersion and High-NA processes for ArF scanners