Zobrazeno 1 - 10
of 17
pro vyhledávání: '"Koichiro Tsujita"'
Autor:
Hiroyuki Ishii, Hidetami Yaegashi, Ryo Nakayama, Kenichi Oyama, Michael C. Smayling, Koichiro Tsujita, Valery Axelrad, Koji Mikami
Publikováno v:
Photomask Japan 2015: Photomask and Next-Generation Lithography Mask Technology XXII.
The pattern splitting algorithm for 1D Gridded-Design-Rules layout (1D layout) for sub-10 nm node logic devices is shown. It is performed with integer linear programming (ILP) based on the conflict graph created from a grid map for each designated pi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::88639afd302c24c5383a0bb518f83168
https://doi.org/10.1117/12.2192529
https://doi.org/10.1117/12.2192529
Autor:
Kenichi Oyama, Hidetami Yaegashi, Hiroyuki Ishii, Koichiro Tsujita, Valery Axelrad, Shohei Yamauchi, Ryo Nakayama, Koji Mikami, Michael C. Smayling
Publikováno v:
SPIE Proceedings.
The CMOS logic 22nm node was the last one done with single patterning. It used a highly regular layout style with Gridded Design Rules (GDR). Smaller nodes have required the same regular layout style but with multiple patterning for critical layers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fcc61d128d7b163bbb6557c010f8e23d
https://doi.org/10.1117/12.2084846
https://doi.org/10.1117/12.2084846
Autor:
Yoshihisa Matsubara, Takashi Nasuno, Wataru Wakamiya, Eiichi Soda, N. Kobayashi, Akiyuki Minami, Hiroshi Tsuda, Hiromasa Kobayashi, Koichiro Tsujita
Publikováno v:
IEICE Transactions on Electronics. :796-803
A novel via chain structure for failure analysis at 65 nm-node fixing OPC using inner and outer via chain dummy patterns has been proposed. The inner dummy is necessary to localize failure site in 200 nm pitch via chain using an optical beam induced
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb8f2c3592fdd71fb4ebbd116e4d8b3b
https://doi.org/10.1093/ietele/e88-c.5.796
https://doi.org/10.1093/ietele/e88-c.5.796
Publikováno v:
SPIE Proceedings.
Highly regular gridded designs are generally seen as a key component for continued advances in lithographic resolution in a time of limited further progress in lithography hardware [1]. With a given process technology tool set, higher pattern density
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::056b9d3f37ce4e12fefa10992355b77b
https://doi.org/10.1117/12.2069353
https://doi.org/10.1117/12.2069353
Autor:
Kenichi Oyama, Valery Axelrad, Arisa Hara, Koichiro Tsujita, Ryo Nakayama, Hidetami Yaegashi, Michael C. Smayling
Publikováno v:
SPIE Proceedings.
CMOS logic at the 22nm node and below is being done with a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes have been demonstrated using a “lines and cuts” approach with good pattern fidelity and process margin, with ex
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f074d54cf41977baf027db17555bc3cd
https://doi.org/10.1117/12.2045667
https://doi.org/10.1117/12.2045667
Publikováno v:
SPIE Proceedings.
Highly regular gridded designs have been generally accepted 1 as a key component for continued advances in lithographic resolution in an era of limited further progress in lithography hardware. With a given process technology tool set, higher pattern
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4963e656bdc86d6733856f5a830907b9
https://doi.org/10.1117/12.2046120
https://doi.org/10.1117/12.2046120
Autor:
Kenichi Oyama, Hidetami Yaegashi, Koichiro Tsujita, Arisa Hara, Michael C. Smayling, Valery Axelrad, Tadashi Arai
Publikováno v:
SPIE Proceedings.
The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A “lines an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3db1a077fc84d5ee2d6885d9d1e75d9c
https://doi.org/10.1117/12.2011329
https://doi.org/10.1117/12.2011329
Autor:
Valery Axelrad, Hidetami Yaegashi, Michael C. Smayling, Kenichi Oyama, Koichiro Tsujita, Hiroyuki Ishii, Ryo Nakayama, Koji Mikami, Tadashi Arai
Publikováno v:
SPIE Proceedings.
An SMO whose optimized source shape and mask pattern can be simple is shown. However the simple solution can be competitive to a solution by complicated source shape and mask pattern. This technology is applied to cut pattern of 1 dimensional GDR lay
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::86ae25e89a4557ec407585517443b275
https://doi.org/10.1117/12.961118
https://doi.org/10.1117/12.961118
Autor:
Ryo Nakayama, Hidetami Yaegashi, Yuichi Gyoda, Kenichi Oyama, Koichiro Tsujita, Michael C. Smayling, Valery Axelrad
Publikováno v:
SPIE Proceedings.
The CMOS logic 22nm node is being done with single patterning and a highly regular layout style using Gridded Design Rules (GDR). Smaller nodes will require the same regular layout style but with multiple patterning for critical layers. A line/cut ap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b87671bb8c8007c38d904c43831bdfce
https://doi.org/10.1117/12.914916
https://doi.org/10.1117/12.914916
Autor:
Kazuhiro Takahashi, Hiroyuki Ishii, Koichiro Tsujita, Yuichi Gyoda, Michael C. Smayling, Tadashi Arai, Valery Axelrad
Publikováno v:
SPIE Proceedings.
A method to resolve 20nm node of SRAM contact layer whose minimum pitch is 90nm with enough process latitude is shown. To achieve the target by single exposure under condition of ArF and 1.35 of NA a way to optimize lithography parameters and layout
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d5fb0c31b0f60e9cbf94c31c1e5e45d
https://doi.org/10.1117/12.878663
https://doi.org/10.1117/12.878663