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A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS

Autor: Koh Jinseok, Gomez Gabriel, Muhammad Khurram, Staszewski R Bogdan, Haroun Baher

Publikováno v: EURASIP Journal on Wireless Communications and Networking, Vol 2006, Iss 1, p 071249 (2006)

We present a discrete-time second-order multibit sigma-delta ADC that filters and decimates by two the input data samples. At the same time it provides gain control function in its input sampling stage. A 4-tap FIR switched capacitor (SC) architectur

Externí odkaz: https://doaj.org/article/769c82e14adb42dda2a59486d01ec4c2

SoC With an Integrated DSP and a 2.4-GHz RF Transmitter.

Autor: Staszewski, Robert B., Staszewski, Roman, Wallberg, John L., Jung, Tom, Hung, Chih-Ming, Koh, Jinseok, Leipold, Dirk, Maggio, Ken, Balsara, Poras T.

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Nov2005, Vol. 13 Issue 11, p1253-1266, 15p, 8 Black and White Photographs, 7 Diagrams, 2 Charts, 1 Graph