Zobrazeno 1 - 10 of 23 pro vyhledávání: '"Kodai Ueyoshi"'
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A 96-MB 3D-Stacked SRAM Using Inductive Coupling With 0.4-V Transmitter, Termination Scheme and 12:1 SerDes in 40-nm CMOS
Autor: Tadahiro Kuroda, Tatsuo Omori, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Kota Shiba, Kodai Ueyoshi
Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 68:692-703
A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter that reduces th
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ae13937be9b5039dc428b878b61372bb
https://doi.org/10.1109/tcsi.2020.3037892
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5
QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS
Autor: Masato Motomura, Kazutoshi Hirose, Tadahiro Kuroda, Kota Ando, Kodai Ueyoshi, Shinya Takamaeda-Yamazaki, Mototsugu Hamada
Publikováno v: IEEE Journal of Solid-State Circuits. 54:186-196
QUEST is a programmable multiple instruction, multiple data (MIMD) parallel accelerator for general-purpose state-of-the-art deep neural networks (DNNs). It features die-to-die stacking with three-cycle latency, 28.8 GB/s, 96 MB, and eight SRAMs usin
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::36232d7c31798ea54bfc9cf00b6d20b1
https://doi.org/10.1109/jssc.2018.2871623
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6
A 3D-Stacked SRAM using Inductive Coupling with Low-Voltage Transmitter and 12:1 SerDes
Autor: Tatsuo Omori, Mototsugu Hamada, Kota Shiba, Shinya Takamaeda-Yamazaki, Tadahiro Kuroda, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Masato Motomura
Publikováno v: ISCAS
A 28.8-GB/s 96-MB 3D-stacked SRAM is presented. A total of eight SRAM dies, designed in a 40-nm CMOS process, are vertically stacked and connected using an inductive coupling wireless link with a low-voltage NMOS push-pull transmitter that reduces th
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::86e053a677c31b146632a2350305cc39
https://doi.org/10.1109/iscas45731.2020.9181008
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7
BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W
Autor: Kentaro Orimo, Haruyoshi Yonekawa, Hiroki Nakahara, Tadahiro Kuroda, Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Tetsuya Asai, Masayuki Ikebe, Shimpei Sato, Masato Motomura, Kota Ando
Publikováno v: IEEE Journal of Solid-State Circuits. 53:983-994
A versatile reconfigurable accelerator architecture for binary/ternary deep neural networks is presented. In-memory neural network processing without any external data accesses, sustained by the symmetry and simplicity of the computation of the binar
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7d440f33db90b54fd5d1141c2c32869c
https://doi.org/10.1109/jssc.2017.2778702
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9
Error Tolerance Analysis of Deep Learning Hardware Using a Restricted Boltzmann Machine Toward Low-Power Memory Implementation
Autor: Yuichiro Mitani, Masato Motomura, Takao Marukame, Alexandre Schmid, Tetsuya Asai, Yusuke Higashi, Masamichi Suzuki, Kodai Ueyoshi
Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 64:462-466
Remarkable hardware robustness of deep learning (DL) is revealed by error injection analyses performed using a custom hardware model implementing parallelized restricted Boltzmann machines (RBMs). RBMs in deep belief networks demonstrate robustness a
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c5b003e76efedbacdfa596006f57b9b0
https://doi.org/10.1109/tcsii.2016.2585675
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10
FPGA Implementation of a Scalable and Highly Parallel Architecture for Restricted Boltzmann Machines
Autor: Tetsuya Asai, Takao Marukame, Masato Motomura, Alexandre Schmid, Kodai Ueyoshi
Publikováno v: Circuits and Systems. :2132-2141
Restricted Boltzmann Machines (RBMs) are an effective model for machine learning; however, they require a significant amount of processing time. In this study, we propose a highly parallel, highly flexible architecture that combines small and complet
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::c7942bc17b689f802565dcc83687bc9d
https://doi.org/10.4236/cs.2016.79185
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