Zobrazeno 1 - 10
of 130
pro vyhledávání: '"Knechtel, Johann"'
Autor:
Bhandari, Jitendra, Chowdhury, Animesh Basak, Nabeel, Mohammed, Sinanoglu, Ozgur, Garg, Siddharth, Karri, Ramesh, Knechtel, Johann
Power side-channel (PSC) analysis is pivotal for securing cryptographic hardware. Prior art focused on securing gate-level netlists obtained as-is from chip design automation, neglecting all the complexities and potential side-effects for security ar
Externí odkaz:
http://arxiv.org/abs/2406.19549
This work investigates the potential of tailoring Large Language Models (LLMs), specifically GPT3.5 and GPT4, for the domain of chip testing. A key aspect of chip design is functional testing, which relies on testbenches to evaluate the functionality
Externí odkaz:
http://arxiv.org/abs/2406.17132
Chip design is about to be revolutionized by the integration of large language, multimodal, and circuit models (collectively LxMs). While exploring this exciting frontier with tremendous potential, the community must also carefully consider the relat
Externí odkaz:
http://arxiv.org/abs/2405.07061
Autor:
Wang, Fangzhou, Wang, Qijing, Alrahis, Lilas, Fu, Bangqi, Jiang, Shui, Zhang, Xiaopeng, Sinanoglu, Ozgur, Ho, Tsung-Yi, Young, Evangeline F. Y., Knechtel, Johann
Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many security threats, like piracy of IC intellectual property or insertion of
Externí odkaz:
http://arxiv.org/abs/2405.05590
Autor:
Bhandari, Jitendra, Nabeel, Mohammed, Mankali, Likhitha, Sinanoglu, Ozgur, Karri, Ramesh, Knechtel, Johann
This paper presents a novel defense strategy against static power side-channel attacks (PSCAs), a critical threat to cryptographic security. Our method is based on (1) carefully tuning high-Vth versus low-Vth cell selection during synthesis, accounti
Externí odkaz:
http://arxiv.org/abs/2402.03196
Autor:
Chowdhury, Animesh Basak, Alrahis, Lilas, Collini, Luca, Knechtel, Johann, Karri, Ramesh, Garg, Siddharth, Sinanoglu, Ozgur, Tan, Benjamin
Oracle-less machine learning (ML) attacks have broken various logic locking schemes. Regular synthesis, which is tailored for area-power-delay optimization, yields netlists where key-gate localities are vulnerable to learning. Thus, we call for secur
Externí odkaz:
http://arxiv.org/abs/2303.03372
We propose TrojanSAINT, a graph neural network (GNN)-based hardware Trojan (HT) detection scheme working at the gate level. Unlike prior GNN-based art, TrojanSAINT enables both pre-/post-silicon HT detection. TrojanSAINT leverages a sampling-based GN
Externí odkaz:
http://arxiv.org/abs/2301.11804
Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, ther
Externí odkaz:
http://arxiv.org/abs/2211.16495
Power side-channel (PSC) attacks are well-known threats to sensitive hardware like advanced encryption standard (AES) crypto cores. Given the significant impact of supply voltages (VCCs) on power profiles, various countermeasures based on VCC tuning
Externí odkaz:
http://arxiv.org/abs/2211.08046
Autor:
Wang, Fangzhou, Wang, Qijing, Fu, Bangqi, Jiang, Shui, Zhang, Xiaopeng, Alrahis, Lilas, Sinanoglu, Ozgur, Knechtel, Johann, Ho, Tsung-Yi, Young, Evangeline F. Y.
Due to cost benefits, supply chains of integrated circuits (ICs) are largely outsourced nowadays. However, passing ICs through various third-party providers gives rise to many threats, like piracy of IC intellectual property or insertion of hardware
Externí odkaz:
http://arxiv.org/abs/2211.07997