Zobrazeno 1 - 10
of 33
pro vyhledávání: '"Knag, Phil"'
Akademický článek
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Autor:
Lin, Chuan-Tung, Wang, Dewei, Zhang, Bo, Chen, Gregory K., Knag, Phil C., Krishnamurthy, Ram Kumar, Seok, Mingoo
Publikováno v:
IEEE Journal of Solid-State Circuits; 2024, Vol. 59 Issue: 3 p960-971, 12p
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
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Autor:
H. Ekin Sumbul, Monodeep Kar, Himanshu Kaul, Knag Phil, Amit Agarwal, Raghavan Kumar, Seongjong Kim, Gregory K. Chen, Steven K. Hsu, Mark A. Anders, Ram Krishnamurthy
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:1082-1092
A binary neural network (BNN) chip explores the limits of energy efficiency and computational density for an all-digital deep neural network (DNN) inference accelerator. The chip intersperses data storage and computation using computation near memory
Autor:
Himanshu Kaul, Amit Agarwal, Seongjong Kim, Knag Phil, Steven K. Hsu, Mark A. Anders, Gregory K. Chen, H. Ekin Sumbul, Ram Krishnamurthy, Raghavan Kumar, Monodeep Kar
Publikováno v:
IEEE Solid-State Circuits Letters. 3:118-121
A 10-nm compute-near-memory (CNM) accelerator augments SRAM with multiply accumulate (MAC) units to reduce interconnect energy and achieve 2.9 8b-TOPS/W for matrix–vector computation. The CNM provides high memory bandwidth by accessing SRAM subarra
Autor:
Ram Krishnamurthy, Sanu Mathew, Himanshu Kaul, H. Ekin Sumbul, Steven K. Hsu, Mark A. Anders, Raghavan Kumar, Vikram B. Suresh, Amit Agarwal, Vivek De, Seongjong Kim, Knag Phil, Gregory K. Chen, Monodeep Kar
Publikováno v:
IEEE Solid-State Circuits Letters. 3:338-341
A 10-nm DNN inference accelerator compresses model size with tabulation hash-based fine-grained weight sharing and increases 8b-compute density by $3.4\times $ to 1.6 TOPS/mm2. The compressed model DNN implements lightweight hashing circuits to compr
Publikováno v:
IEEE Journal of Solid-State Circuits; 2023, Vol. 58 Issue: 4 p1117-1128, 12p
Autor:
Amit Agarwal, Monodeep Kar, Mark A. Anders, H. Ekin Sumbul, Knag Phil, Seongjong Kim, Gregory K. Chen, Steven K. Hsu, Ram Krishnamurthy, Himanshu Kaul, Raghavan Kumar
Publikováno v:
VLSI Circuits
A 10nm digital Binary Neural Network (BNN) chip implements 1b activations and weights for compute density of 418TOPS/mm2 and memory density of 414KB/mm2. The chip achieves an energy efficiency of 617TOPS/W by leveraging Compute Near Memory (CNM), par
Autor:
Gregory K. Chen, Sanu Mathew, Amit Agarwal, Iqbal R. Rajwani, Steven K. Hsu, Mark A. Anders, Vikram B. Suresh, Simeon Realov, Knag Phil, Ram Krishnamurthy, Satish Damaraju, Vivek De, Monodeep Kar, Sumbul Huseyin Ekin, Himanshu Kaul, Raghavan Kumar
Publikováno v:
VLSI Circuits
Low-clock-power digital standard cell IPs in 10nm CMOS, featuring low-power shared-clock (LPSC) flip-flops (FFs), LPSC back-to-back (B2B) FFs, and pass-gate (PG) integrated clock gates (ICGs), achieve up to 14%, 45%, and 14% measured clock energy imp
Autor:
Jonathan Byrne, Gregory K. Chen, Monodeep Kar, Sumbul Huseyin Ekin, David Moloney, Vivek De, Knag Phil, Raghavan Kumar, Mark A. Anders, Steven K. Hsu, Luca Sarti, Himanshu Kaul, Ram Krishnamurthy, Amit Agarwal
Publikováno v:
VLSI Circuits
A ray-casting accelerator in 10nm CMOS simultaneously casts multiple rays in spatial proximity to exploit voxel data-locality, featuring a near-memory search for voxel address overlaps and opportunistic approximate trilinear interpolation for energy