Zobrazeno 1 - 10
of 59
pro vyhledávání: '"KleinOsowski, A."'
Autor:
K. KleinOsowski, David J. Lilja, A.J. KleinOsowski, P. Ranganath, V.V. Pai, M. Subramony, V. Rangarajan
Publikováno v:
IEEE Transactions On Nanotechnology. 5:575-586
Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d92bc1951f00ae295d098031f19d82ab
https://doi.org/10.1109/tnano.2006.880901
https://doi.org/10.1109/tnano.2006.880901
Autor:
Ethan H. Cannon, T. Swann, A. J. Kleinosowski, Tony Amort, Roger Brees, J. Wert, Manuel Cabanas-Holmen, S. Fischer, Jon Ballast, Barry Meaker
Publikováno v:
IEEE Transactions on Nuclear Science. 58:2726-2733
We describe the approach used to calculate and verify on-orbit upset rates of radiation hardened microprocessors. System designers use these error rates to choose between microprocessors and add appropriate system-level recovery and redundancy.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5741ff45c82d7289c1431857b255366
https://doi.org/10.1109/tns.2011.2168978
https://doi.org/10.1109/tns.2011.2168978
Autor:
A. J. Kleinosowski, Manuel Cabanas-Holmen, J. Killens, Jon Ballast, Ethan H. Cannon, J. Socha
Publikováno v:
IEEE Transactions on Nuclear Science. 56:3505-3510
A complex processor was synthesized using an RHBD cell library and fabricated in a commercial 90 nm CMOS technology. Single Event Effects testing revealed transients on the clock and global reset signals. These critical circuits will receive addition
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9cfd04adac5c16eabae23b42a112a81b
https://doi.org/10.1109/tns.2009.2034314
https://doi.org/10.1109/tns.2009.2034314
Autor:
D. DeSalvo, M. Baze, M. Dooley, B. Hughlock, B. Rasmussen, K. Gerst, A. Le, M. Yoo, D. Nardi, I. Ojalvo, K. Kohnen, E. Zayas, D. Sunderland, R.D. Jobe, B. Jeppson, J. Truong, D.L. Hansen, A. Kleinosowski, K. Amador, E.J. Miller, D. Wong
Publikováno v:
IEEE Transactions on Nuclear Science. 56:3542-3550
Utilizing an application specific integrated circuit (ASIC) with 140 different shift chains, and a wide variety of test modes, a design of experiments (DOE) approach was used to characterize a commercial 90 nm CMOS technology for its sensitivity to s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::935091bcd811e1141eb5966d1dabe6b4
https://doi.org/10.1109/tns.2009.2031972
https://doi.org/10.1109/tns.2009.2031972
Publikováno v:
IEEE Transactions on Nuclear Science. 55:3461-3466
This paper presents modeling and measurements of single event transients in a commercial 45 nm SOI device technology. SETs in clock circuits and pass gates can cause upsets in circuit structures hardened against single event upsets.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1229ff30cbaeca2be40186f4754451d8
https://doi.org/10.1109/tns.2008.2005191
https://doi.org/10.1109/tns.2008.2005191
Publikováno v:
IBM Journal of Research and Development. 52:255-263
As semiconductor devices decrease in size, soft errors are becoming a major issue that must be addressed at all stages of product definition. Even before prototype silicon chips are available for measuring, modeling must be able to predict soft-error
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::de61580d0f7bad47b587138cbf98a9d4
https://doi.org/10.1147/rd.523.0255
https://doi.org/10.1147/rd.523.0255
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 8:145-152
This paper describes modeling and hardware results of how the soft-error rate (SER) of a 65-nm silicon-on-insulator SRAM memory cell changes over time, as semiconductor aging effects shift the SRAM cell behavior. This paper also describes how the SER
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cef4a94df3735311de7b9784a04bf161
https://doi.org/10.1109/tdmr.2007.912983
https://doi.org/10.1109/tdmr.2007.912983
Autor:
A.J. Kleinosowski, Ethan H. Cannon, C. Plettner, David F. Heidel, M.S. Gordon, Philip J. Oldiges, R.D. Rose, H.H.K. Tang, Kenneth P. Rodbell
Publikováno v:
IEEE Transactions on Nuclear Science. 54:2021-2027
This paper describes techniques for mitigating single event upsets in master-slave flip-flop latches in 65 nm SOI device technology. Techniques are explained, modeled, and measured with hardware experiments.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5869de10b745d2b61d54192c968e0412
https://doi.org/10.1109/tns.2007.909707
https://doi.org/10.1109/tns.2007.909707
Publikováno v:
IEEE Transactions on Nuclear Science. 53:3321-3328
This paper describes a technique for modeling single-event upsets due to ionizing radiation in a partially depleted silicon-on-insulator (SOI) MOSFET device. Two current pulses are used, one connected between the drain and body of the device, and the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7b90ae3822352ceb72a0f9f1cfe77911
https://doi.org/10.1109/tns.2006.884353
https://doi.org/10.1109/tns.2006.884353
Publikováno v:
DSN
Advanced molecular nanotechnology devices are expected to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We introduce the recursive nanobox processor grid as an applicat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::398c2420cf09ef821c773104b016e7b7
https://doi.org/10.1109/dsn.2004.1311887
https://doi.org/10.1109/dsn.2004.1311887