Výsledky vyhledávání - "Kiyoshi Oguri"

Pipelined FPGA Implementation of a Wave-Front-Fetch Graph Cut System

Autor: Kiyoshi Oguri, Ryo Kamasaka, Naofumi Yoshinaga, Yuichiro Shibata

Publikováno v: Advances in Intelligent Systems and Computing ISBN: 9783030223533
CISIS

The current mainstream method for stereo vision is to find corresponding points of two-dimensional images obtained from multiple cameras and restore three-dimensional information using the principle of triangulation. However, the occlusion problem of

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9caa33eb79ac685ab21570d9af31ceed
https://doi.org/10.1007/978-3-030-22354-0_38

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Power Performance Profiling of 3-D Stencil Computation on an FPGA Accelerator for Efficient Pipeline Optimization

Autor: Koji Okina, Kota Fukumoto, Yuichiro Shibata, Kiyoshi Oguri, Rie Soejima

Publikováno v: ACM SIGARCH Computer Architecture News. 43:9-14

This paper discusses power-performance optimization for 3-D stencil computing on a stream-oriented FPGA accelerator with highlevel synthesis. Taking a heat conduction simulation and an FDTD electromagnetic field simulation as benchmark applications,

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::920f497c2d6403174a6711e1c25465d6
https://doi.org/10.1145/2927964.2927967

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An FPGA-oriented Graph Cut Algorithm for Accelerating Stereo Vision

Autor: Kiyoshi Oguri, Ryo Kamasaka, Yuichiro Shibata

Publikováno v: ReConFig

Stereo vision, which reconstructs 3-D information from images obtained by two cameras, is one of the topics most actively addressed in the field of computer vision. While the stereo vision problem can be formulated and solved as an energy minimizatio

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8aede4815f072dcfee3229c4f1c1d1e3
https://doi.org/10.1109/reconfig.2018.8641737

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Discussion on High Level Synthesis FPGA Design of Camera Calibration

Autor: Kiyoshi Oguri, Yuichiro Shibata, Hiroki Nagayama, Kazuya Uetsuhara

Publikováno v: Advances in Intelligent Systems and Computing ISBN: 9783319936581
CISIS

Geometric camera calibration plays a key role in machine vision to detect and measure objects. This work presents the high level synthesis (HLS) design of a camera calibration algorithm on an FPGA. By optimizing the C description, we were able to imp

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6a94b0dbbc0ba678eec30e39befb9e4d
https://doi.org/10.1007/978-3-319-93659-8_48

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FPGA implementation of a real-time super-resolution system with a CNN based on a residue number system

Autor: Yuichiro Shibata, Taito Manabe, Kiyoshi Oguri

Publikováno v: FPT

A super-resolution technology is used for filling the gap between high-resolution displays and lower-resolution images. One of various algorithms to interpolate the lost information is to use a convolutional neural network (CNN). This paper shows an

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2dbf0906c717e7e01ce9f3117533397d
https://doi.org/10.1109/fpt.2017.8280165

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Power Performance Analysis of FPGA-Based Particle Filtering for Realtime Object Tracking

Autor: Kiyoshi Oguri, Theint Theint Thu, Yuichiro Shibata, Akane Tahara, Yoshiki Hayashida

Publikováno v: Advances in Intelligent Systems and Computing ISBN: 9783319615653
CISIS

Real-time image processing with a compact FPGA-based architecture plays a key role in dynamic state-space models. This paper presents an energy efficient FPGA acceleration architecture of a particle filter, which is based on stream processing structu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ac7fdcffd4930f3fadfd0d34c0fc942d
https://doi.org/10.1007/978-3-319-61566-0_41

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HLS-Based FPGA Acceleration of Building-Cube Stencil Computation

Autor: Yuichiro Shibata, Kiyoshi Oguri, Rie Soejima

Publikováno v: Advances in Intelligent Systems and Computing ISBN: 9783319615653
CISIS

This paper presents design and implementation of a framework for high-level synthesis (HLS), which allows easy description and acceleration of stencil computation with building-cube method (BCM) on FPGAs. The BCM is one of adaptive mesh refinement me

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7dcb4bffdabeb5bb4f80acacaa096659
https://doi.org/10.1007/978-3-319-61566-0_42

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