Výsledky vyhledávání - "Kiyoko Ikeuchi"

Process parameter and logic extraction for complex manufacturing job shops leveraging network analytics and Digital Twin modelling techniques

Autor: Dávid Gyulai, Kiyoko Ikeuchi, Júlia Bergmann, Suraj Rao, Botond Kádár

Publikováno v: CIRP Annals.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8afeffeb6ebda471ac434a311ec4b86d
https://doi.org/10.1016/j.cirp.2023.03.032

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Novel Mold-free Fan-out Wafer Level Package using Silicon Wafer

Autor: Anu Srivastava, Khanh Tran, Kiyoko Ikeuchi, Ricky Agrawal, Vivek Sridharan, Viren Khandekar, Amit S. Kelkar

Publikováno v: International Symposium on Microelectronics. 2016:000410-000414

The ever increasing demand for high levels of integration and miniaturization has created new transistor nodes, shrunk redistribution line width/space, and driven a reduction in solder bump pitch. This has created the need for Fan-out packaging. This

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f2bc585f4c0417e6ab1d268b33f4836d
https://doi.org/10.4071/isom-2016-tha23

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Studies of the Toxicological Potential of Capsinoids, XII: Pharmacokinetic Study of Capsinoid-Containing CH-19 Sweet Extract in Rats

Autor: Satoko Ueno, Bruce K. Bernard, Yoshiaki Shirai, Kazuyuki Ubukata, Kiyoko Ikeuchi, Akira Nakayama, Ryuichi Mihara

Publikováno v: International Journal of Toxicology. 29:15S-21S

Pharmacokinetics of the main capsinoid components of CH-19 Sweet extract (capsiate, dihydrocapsiate, and nordihydrocapsiate) were investigated in rats receiving a single gavage dose of extract containing 10 or 100 mg of capsinoids per kilogram in med

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::7c58a9ccd60e6db7963cdf8a8642acb5
https://doi.org/10.1177/1091581809359427

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3D heterogeneous integration for analog

Autor: Arkadii V. Samoilov, Peter McNally, Tie Wang, Joy T. Jones, Nicole D. Kerness, Kiyoko Ikeuchi, Joseph P. Ellul, Stanley Barnett, Khanh Tran, Tyler Parent, Anu Srivastava, Tiao Zhou

Publikováno v: 2013 IEEE International Electron Devices Meeting.

We illustrate capabilities of 3D integration for analog applications through both wafer-level and packaging technologies. Examples of wafer-level 3D integration include integrated capacitors and optical sensors. Integrated Si capacitors demonstrate t

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::dce13de344c6eaed4faa593ae0334ece
https://doi.org/10.1109/iedm.2013.6724688

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