Zobrazeno 1 - 10
of 75
pro vyhledávání: '"Kisik Choi"'
Autor:
Nathan Ip, Michael P. Belyansky, Christopher Netzband, Norifumi Kohama, Richard Johnson, Shobha Hosadurga, Jack Wong, John C. Arnold, Kisik Choi, Wai Kin Li, Indira Seshadri, Luciana Meli, Ilseok Son
Publikováno v:
Metrology, Inspection, and Process Control XXXVII.
Autor:
Phillip J. Restle, John G. Massey, Paul C. Jamison, Sebastian Naczas, Eric Liu, Alex Romero, Vijay Narayanan, Shanti Pancharatnam, Hemanth Jagannathan, Kisik Choi, Joshua M. Rubin, Nicolas Loubet, P.J. Chen, Eduard A. Cartier, Takashi Ando
Publikováno v:
ECS Transactions. 97:81-92
We demonstrate a MIM capacitor structure using ZrO2 for the dielectric layer which exhibits a 25% capacitance increase (from ~43fF/mm2 to >55fF/mm2 for a ~55A film) with minimal leakage current increase compared to Hf based dielectrics, extending the
Autor:
Kangguo Cheng, J. Maniscalco, O. van der Straten, Huai Huang, Kisik Choi, Nicholas A. Lanzillo, Christopher J. Penny, Theodorus E. Standaert, Motoyama Koichi, C.-C. Yang
Publikováno v:
IEEE Electron Device Letters. 40:1804-1807
We investigate the performance and reliability characteristics of Cu interconnects with Ta-based barrier layers and Co wetting layers at 7nm node dimensions with a focus on the impacts of reducing the Co thickness from 30A down to 10A. We demonstrate
Autor:
Balasubramanian S. Pranatharthi Haran, B. Peethala, Kedari Matam, Kisik Choi, Nicholas A. Lanzillo, J. Casey, L. Chang, Terry A. Spooner, D. Janes, David L. Rath, Benjamin D. Briggs, Donald F. Canaperi, M. Packiam, Devika Sil, Hosadurga Shobha, Ryan Kevin J
Publikováno v:
2021 IEEE International Interconnect Technology Conference (IITC).
The Fully aligned via scheme (FAV) is known to mitigate the via misalignment issues that drive a lower Vmax and limits the contact area between the via and the underlying line. Even though the overall benefits of FAV are well known, the key detractor
Autor:
O. van der Straten, Scott DeVries, H. Seo, Motoyama Koichi, J. Maniscalco, Kisik Choi, Hsiang-Jen Huang, T. Shen, T. Wu, T. Bae, Nicholas A. Lanzillo, Kyu-Charn Park, Kangguo Cheng, S. Hosadurga, Terry A. Spooner
Publikováno v:
2020 IEEE International Interconnect Technology Conference (IITC).
It has been confirmed that Co diffusion from the cap into a Ru liner (resulting in Co depletion at the top of Cu lines) is the root cause of EM degradation for Cu interconnects in the case of using a combination of Ru liner and selective Co cap. Incr
Autor:
Vimal Kamineni, Junli Wang, Susan Su Chen Fan, Andre Labonte, Ruilong Xie, Dinesh Gupta, Raja Muthinti, Juntao Li, Dechao Guo, Ryan Kevin J, B. Peethala, Richard Conte, Christopher Prindle, Veeraraghavan S. Basker, Shanti Pancharatnam, Kangguo Cheng, Albert M. Young, Stan D. Tsai, Huiming Bu, H. P. Amanapu, Chanro Park, Balasubramanian S. Haran, Robert R. Robison, Nicolas Loubet, Y. Liang, Huimei Zhou, Kisik Choi, Richard A. Conti, Andreas Knorr, Cave Nigel, Adra Carr, Saraf Iqbal Rashid, Andrew M. Greene, Michael P. Belyansky, Hao Tang, Mark Raymond
Publikováno v:
2019 Symposium on VLSI Technology.
We demonstrate a novel self-aligned gate contact (SAGC) scheme with conventional oxide/nitride materials that allows superior process integration for scaling while simplifying the SRAM cross-couple wiring. We show that the key feature to avoid both g
Autor:
Christian Lavoie, Curtis Durfee, Edward J. Nowak, Stan D. Tsai, Dechao Guo, W. Wang, Vimal Kamineni, Adra Carr, Gen Tsutsui, H. P. Amanapu, Jie Yang, Walter Kleemeier, Kisik Choi, Oleg Gluschenkov, Samuel S. Choi, Saraf Iqbal Rashid, Dinesh Gupta, F. Lie, Huiming Bu, Lan Yu, Andreas Knorr, Tenko Yamashita, Heng Wu, Zuoguang Liu, Christopher Prindle, Cave Nigel, Ryan Kevin J, Jay W. Strane, Kevin W. Brew, Chengyu Niu, Y. Liang, Balasubramanian S. Pranatharthi Haran, Mukesh Khare, Shogo Mochizuki, James J. Demarest
Publikováno v:
2018 IEEE International Electron Devices Meeting (IEDM).
This work thoroughly investigates the external parasitic resistance in advanced FinFET technology. The optimization of the parasitic resistance is systematically examined in terms of 1) source/drain epi resistance, 2) contact resistance and 3) middle
Autor:
Alex Romero, John G. Massey, Joshua M. Rubin, Vijay Narayanan, Phillip J. Restle, Paul C. Jamison, Nicolas Loubet, Sebastian Naczas, Eric Liu, Kisik Choi, P.J. Chen, Shanti Pancharatnam, Eduard A. Cartier, Takashi Ando, Hemanth Jagannathan
Publikováno v:
ECS Meeting Abstracts. :1656-1656
We demonstrate a MIM capacitor structure using ZrO2 for the dielectric layer which exhibits a 25% capacitance increase (from ~43fF/mm2 to >55fF/mm2 for a ~55 Å film) with minimal leakage current increase compared to Hf based dielectrics, extending t
Autor:
Hemant Dixit, Mark Raymond, T. Abrams, Stan D. Tsai, Heng Wu, Ryan Kevin J, Vimal Kamineni, Praneet Adusumilli, H. P. Amanapu, Chengyu Niu, Jin Cho, R. Xiel, Y. Liang, Aniruddha Konar, X. Lin, Dechao Guo, Adra Carr, Samuel S. Choi, S. Fan, Nicholas A. Lanzillo, Kisik Choi, James J. Kelly
Publikováno v:
2018 IEEE International Interconnect Technology Conference (IITC).
Continuous CMOS scaling is being driven by innovation of novel device architectures to improve device performances at lower power consumption [1]. However, middle-of-the-line (MOL) continues to be a key performance and yield detractor for scaling. To
Autor:
Oleg Gluschenkov, Zuoguang Liu, Chengyu Niu, Andreas Knorr, Tenko Yamashita, Jay W. Strane, Mukesh Khare, Gen Tsutsui, Chris M. Prindle, Abraham Arceo, Indira Seshadri, Bruce Miao, A. Petrescu, Stan D. Tsai, Curtis Durfee, Soon-Cheon Seo, Adra Carr, Jie Yang, Walter Kleemeier, Kisik Choi, F. Lie, W. Wang, Rama Divakaruni, Chanro Park, Mark Raymond, Heng Wu, Huiming Bu, Dechao Guo, Anuja DeSilva, George Yang, Dinesh Gupta, Muthumanickam Sankarapandian, Praneet Adusumilli, Sam Choi, Kerem Akarvardar
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional appr