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pro vyhledávání: '"Kishinevsky, Michael"'
The validation process for microprocessors is a very complex task that consumes substantial engineering time during the design process. Bugs that degrade overall system performance, without affecting its functional correctness, are particularly diffi
Externí odkaz:
http://arxiv.org/abs/2303.15280
Network-on-Chip (NoC) congestion builds up during heavy traffic load and cripples the system performance by stalling the cores. Moreover, congestion leads to wasted link bandwidth due to blocked buffers and bouncing packets. Existing approaches throt
Externí odkaz:
http://arxiv.org/abs/2302.12779
Autor:
Mandal, Sumit K., Tong, Jie, Ayoub, Raid, Kishinevsky, Michael, Abousamra, Ahmed, Ogras, Umit Y.
Fast and accurate performance analysis techniques are essential in early design space exploration and pre-silicon evaluations, including software eco-system development. In particular, on-chip communication continues to play an increasingly important
Externí odkaz:
http://arxiv.org/abs/2108.09534
Autor:
Barboza, Erick Carvajal, Jacob, Sara, Ketkar, Mahesh, Kishinevsky, Michael, Gratz, Paul, Hu, Jiang
Processor design validation and debug is a difficult and complex task, which consumes the lion's share of the design process. Design bugs that affect processor performance rather than its functionality are especially difficult to catch, particularly
Externí odkaz:
http://arxiv.org/abs/2011.08781
Autor:
Mandal, Sumit K., Ogras, Umit Y., Doppa, Janardhan Rao, Ayoub, Raid Z., Kishinevsky, Michael, Pande, Partha P.
Dynamic resource management has become one of the major areas of research in modern computer and communication system design due to lower power consumption and higher performance demands. The number of integrated cores, level of heterogeneity and amo
Externí odkaz:
http://arxiv.org/abs/2008.09728
Priority-aware networks-on-chip (NoCs) are used in industry to achieve predictable latency under different workload conditions. These NoCs incorporate deflection routing to minimize queuing resources within routers and achieve low latency during low
Externí odkaz:
http://arxiv.org/abs/2008.03904
Networks-on-Chip (NoCs) used in commercial many-core processors typically incorporate priority arbitration. Moreover, they experience bursty traffic due to application workloads. However, most state-of-the-art NoC analytical performance analysis tech
Externí odkaz:
http://arxiv.org/abs/2007.13951
Autor:
Gupta, Ujjwal, Babu, Manoj, Ayoub, Raid, Kishinevsky, Michael, Paterna, Francesco, Gumussoy, Suat, Ogras, Umit
Publikováno v:
in IEEE Transactions on Computers, vol. 67, no. 12, pp. 1677-1691, 1 Dec. 2018
Approximately 18 percent of the 3.2 million smartphone applications rely on integrated graphics processing units (GPUs) to achieve competitive performance. Graphics performance, typically measured in frames per second, is a strong function of the GPU
Externí odkaz:
http://arxiv.org/abs/2003.11740
Networks-on-chip (NoCs) have become the standard for interconnect solutions in industrial designs ranging from client CPUs to many-core chip-multiprocessors. Since NoCs play a vital role in system performance and power consumption, pre-silicon evalua
Externí odkaz:
http://arxiv.org/abs/1908.02408
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