Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Kirti Bhanushali"'
Publikováno v:
IEEE Journal of Radio Frequency Identification. 5:317-323
This paper presents a compact and largely digital UHF EPC Gen2-compatible RFID implemented using digital IP blocks that are easily portable. This is the first demonstration of a digital Gen2-compatible RFID tag chip with an area of $125{\mu }\text{m}
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::575537e74f56b06a0c3cb859124c457b
https://doi.org/10.1109/jrfid.2021.3087448
https://doi.org/10.1109/jrfid.2021.3087448
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:406-418
Reducing circuit design cost and eliminating over-design margin are the two challenges for advancing the Internet of Things (IoT). An RF-dc rectifier and storage capacitors consume 25% or more of the chip area for cost-sensitive power-harvesting-enab
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30506c61ef520acd4cc9e7f0f42224fc
https://doi.org/10.1109/tcsi.2017.2715321
https://doi.org/10.1109/tcsi.2017.2715321
Publikováno v:
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Conventional RFID circuits use area-inefficient rectifiers and storage capacitors, and the latter do not scale with technology. These blocks can be eliminated by using a cost-efficient RF-only logic approach, which introduces a power consumption trad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4f322f321014863aea149add4575a7dc
https://doi.org/10.1109/s3s.2018.8640165
https://doi.org/10.1109/s3s.2018.8640165
Publikováno v:
IEEE RFID
AC-DC rectifier and storage capacitors take up 25% or more of chip area for cost-sensitive passive RFID tags. In this work, we show that these components can be eliminated by utilizing a RF-only circuit structure. Therefore, the chip would be smaller
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1eacb14e82734d403220c0746d13fb19
https://doi.org/10.1109/rfid.2016.7488013
https://doi.org/10.1109/rfid.2016.7488013
Autor:
Kirti Bhanushali, W. Rhett Davis
Publikováno v:
ISPD
This paper discusses design rules and layout guidelines for an open source predictive process design kit (PDK) for multi-gate 15nm FinFET devices. Additional design rules are introduced considering process variability, and challenges involved in fabr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d148f0e98785006cf3779369c506adf9
https://doi.org/10.1145/2717764.2717782
https://doi.org/10.1145/2717764.2717782