Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Kirklen Henson"'
Autor:
Małgorzata Jurczak, Ivan Pollentier, Simone Severi, Kirklen Henson, Anne Lauwers, Richard Lindsay, Marc Scaekers, Aude Rotschild, Sofie Mertens, Emmanuel Augendre, Rita Rooyackers, Anabela Veloso, An de Keersgieter
Publikováno v:
Journal of Telecommunications and Information Technology, Iss 1 (2005)
The current trend in scaling transistor gate length below 60 nm is posing great challenges both related to process technology and circuit/system design. From the process technology point of view it is becoming increasingly difficult to continue scali
Externí odkaz:
https://doaj.org/article/1942528edf34498f8916cdd82a0e962e
Autor:
Johan Vertommen, Lars-Ake Ragnarsson, M.M. Heyns, G.S. Lujan, J.C. Hooker, Kirklen Henson, R.J.P. Lander, J.D. Chen, Wilman Tsai, Wim Deweerd, Tom Schram, K. De Meyer, S. De Gendt
Publikováno v:
Microelectronics Reliability. 45:779-782
Direct-etched HfO2/TaN nMOS transistors were fabricated. The performance of the transistors with aggressively scaled EOT is comparable or better than that of SiO2/poly transistors. The performance enhancement requires a combination of EOT scaling and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b36e58b1cb13f5e926912422aeded2c4
https://doi.org/10.1016/j.microrel.2004.11.050
https://doi.org/10.1016/j.microrel.2004.11.050
Publikováno v:
Solid-State Electronics. 48:617-625
In this paper, a model for describing tunneling from Si inversion layers is discussed. The model accounts for the quantization effects at the silicon/dielectric interface and is able to closely follow the self-consistent calculation of the potential
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8965973e10c3c7e73c2a670bb291936
https://doi.org/10.1016/j.sse.2003.09.031
https://doi.org/10.1016/j.sse.2003.09.031
Autor:
Stefan Kubicek, Maarten Rosmeulen, Nadine Collaert, Kirklen Henson, H. van Meer, K. De Meyer, J.-H. Lyu
Publikováno v:
IEEE Electron Device Letters. 21:133-136
The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel-length of the MOS transistor. This method assumes the effective mobility of a long channel and a short channel t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e2db8ebaa2309f9c7f2d74807fcf6b8
https://doi.org/10.1109/55.823579
https://doi.org/10.1109/55.823579
Autor:
C.J.J. Dachs, Tom Schram, R. J. P. Lander, B. Kaczer, S. Biesemans, J.-L. Everaert, M. Demand, Zsolt Tokei, Werner Boullart, Johan Vertommen, Stephan Beckx, J.C. Hooker, Kirklen Henson, O. Richard, Hugo Bender, F. N. Cubaynes, B. Coenegrachts, M. Jurczak, W. Vandervorst, Monja Kaiser, Wim Deweerd
Publikováno v:
IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
We demonstrate for the first time that nMOS devices with PVD TaN gate on 1.2 nm EOT SiON can be fabricated with high drive currents. On state currents of 1150 /spl mu/A//spl mu/m (I/sub off/ < 10 nA//spl mu/m) at 1.2 V and 810 /spl mu/A//spl mu/m (I/
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a446618b6aa9a2361273ee79a3341304
https://doi.org/10.1109/iedm.2004.1419312
https://doi.org/10.1109/iedm.2004.1419312
Autor:
C. Dachs, Rita Rooyackers, O. Richard, A. De Keersgieter, Malgorzata Jurczak, Kirklen Henson, Eddy Kunnen
Publikováno v:
Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).
In this work, we propose a new triple junction approach for aggressively scaled CMOS transistors. It is formed by means of conventional ion implantation in three phases: before offset spacer (LDD), after offset spacer (MDD) and after second spacers (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fcc48711d9655210ed05724ba77c888f
https://doi.org/10.1109/essder.2004.1356510
https://doi.org/10.1109/essder.2004.1356510
Autor:
J. Chen, Yasuhiro Shimamoto, Johan Vertommen, Robin Degraeve, P. Bajolet, Werner Boullart, S. Lin, Hugo Bender, W. Deweerdt, W. Tsai, Stefan Kubicek, J. Westlinder, H. De Witte, E. Young, Stephan Beckx, G.S. Lujan, Martine Claes, Chao Zhao, Vincent Cosnier, Thomas Witters, Kirklen Henson, V. Kaushik, A. Kerber, Thomas Kauerauf, Thierry Conard, J.W. Maes, O. Richard, J. Petry, J. Kluth, Pieter Blomme, L. Lucci, Luigi Pantisano, Wilfried Vandervorst, Bert Brijs, Martin A. Green, M.M. Heyns, E. Rohr, Tom Schram, L. Date, S.E. Jang, Annelies Delabie, B. Coenegrachts, J. Mentens, S. De Gendt, S. Passefort, Y. Manabe, Matty Caymax, D. Pique, Eduard A. Cartier, S. Van Elshocht, P. Van Doorne, R. J. Carter, Guido Groeseneken
Publikováno v:
2003 International Symposium on VLSI Technology, Systems and Applications. Proceedings of Technical Papers. (IEEE Cat. No.03TH8672).
High-k dielectric layers are deposited using ALD or MOCVD. Most of the work focused on Hf-based high-k dielectrics, either as pure HfO/sub 2/, as silicate or mixed with Al/sub 2/O/sub 3/. In some cases nitrogen is added to improve the high-temperatur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec514261c95b67f771635fe12a0a496a
https://doi.org/10.1109/vtsa.2003.1252599
https://doi.org/10.1109/vtsa.2003.1252599
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
The layout of FinFETs patterned with direct lithography and spacer lithography are analysed from a circuit density perspective. Requirements on the height of the fin to obtain competitive layout density are derived. Spacer lithography will be require
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4a630819d2cdcd89b7bab314c02ec57f
https://doi.org/10.1109/essderc.2003.1256830
https://doi.org/10.1109/essderc.2003.1256830
Autor:
Stefan Kubicek, Richard Lindsay, F.N. Cubaynes, C.J.J. Dachs, Z.M. Rittersma, J.C. Hooker, Josine Loo, Gerben Doornbos, Kirklen Henson, R. J. P. Lander, Youri Victorovitch Ponomarev, R. Surdeanu
Publikováno v:
Electrical Performance of Electrical Packaging (IEEE Cat. No. 03TH8710).
A CMOS process is developed in a research environment for integration studies of sub-50 nm MOSFETs with high-k (HiK) dielectrics, metal gates (MG), ultra-shallow junctions with laser thermal annealing (LTA), raised source/drain (RSD) and novel device
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e84eb6a8fa471d0341ea0788c1a513a3
https://doi.org/10.1109/essderc.2003.1256802
https://doi.org/10.1109/essderc.2003.1256802
Autor:
Serge Biesemans, Stefan Kubicek, Anabela Veloso, K.G. Anil, J.-F. de Marneffe, Tom Schram, Katia Devriendt, Anne Lauwers, Kirklen Henson, Stephan Brus, Emmanuel Augendre
Publikováno v:
Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For n
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::342a1b07f52d025c790dc1263e83f003
https://doi.org/10.1109/vlsit.2004.1345472
https://doi.org/10.1109/vlsit.2004.1345472