An Embedded DRAM With a 143-MHz SRAM Interface Using a Sense-Synchronized Read/Write.

Autor: Taito, Yasuhiko, Tanizaki, Tetsushi, Kinoshita, Mitsuya, Igaue, Futoshi, Fujino, Takeshi, Arimoto, Kazutami

Publikováno v: IEEE Journal of Solid-State Circuits; Nov2003, Vol. 38 Issue 11, p1967-1973, 7p, 7 Black and White Photographs, 11 Diagrams, 2 Charts, 1 Graph