Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Kingsuk Maitra"'
Publikováno v:
IEEE Transactions on Electron Devices. 59:72-78
In this paper, we investigate the optimization of device layout and embedded source/drain (eS/D) shape profile for strain engineered 22-nm node Si and SiGe p-channel trigate field-effect transistors by finite-element method simulations. A nested trig
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7d5bbee8bfb03e8542ebee05bcba6214
https://doi.org/10.1109/ted.2011.2171968
https://doi.org/10.1109/ted.2011.2171968
Opportunities and Challenges of FinFET as a Device Structure Candidate for 14nm Node CMOS Technology
Autor:
Vamsi Paruchuri, Andres Bryant, Bruce B. Doris, Tenko Yamashita, Hiroshi Sunamura, Effendi Leobandung, Hemanth Jagannathan, Junli Wang, Atsuro Inada, Theodorus E. Standaert, Pranita Kulkarni, Robert J. Miller, Johnathan E. Faltermeier, Kingsuk Maitra, Huiming Bu, Veeraraghavan S. Basker, James A. O’Neill, Sivananda K. Kanakasabapathy, Chung-Hsun Lin, T. Yamamoto, Chun-Chen Yeh, Jin Cho, Mukesh Khare
Publikováno v:
ECS Transactions. 34:81-86
FinFET is a promising device candidate for 14nm node CMOS technology. We have developed FinFET device showing superior short channel control at 25nm gate length. This FinFET device featuring gate first high-k/metal gate and merged Epi source/drain pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3e339ce32c67c3b83707e7e70c7cdb6b
https://doi.org/10.1149/1.3567563
https://doi.org/10.1149/1.3567563
Publikováno v:
IEEE Transactions on Electron Devices. 55:3175-3183
We evaluate the performance of a novel fast characterization methodology for NBTI and PBTI measurements. We show that the use of a programmable PCI card in combination with linear current amplifiers provides the following means: (a) to perform short
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95926252c35c02ca7843b9da1b0822b3
https://doi.org/10.1109/ted.2008.2004853
https://doi.org/10.1109/ted.2008.2004853
Autor:
A. Marathe, Rune Hartung Jensen, K. Srinivasan, Brian Keith Langendorf, V. Jadhav, S. Chen, Julia Purtell, Kingsuk Maitra, Raj N. Master, Tung Thanh Nguyen, Ranjit Gannamani
Publikováno v:
IRPS
Proximity to the touch sensitive display in thin form factor mobile devices puts a stringent upper limit on the temperature (and hence the V MAX ) at which the SOC may be operated, making the industrial design sometimes limited by the thermals, rathe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e8d848bd77f2486c46e00db913f3f2e0
https://doi.org/10.1109/irps.2015.7112708
https://doi.org/10.1109/irps.2015.7112708
Autor:
Barry Linder, E. Cartier, P. Jamison, John C. Arnold, Vijay Narayanan, Evgeni Gusev, Roy A. Carruthers, Vamsi Paruchuri, Kingsuk Maitra, Dianne L. Lacey, Martin M. Frank, D.C. La Tulipe, Michelle L. Steen
Publikováno v:
IEEE Electron Device Letters. 27:591-594
The performance of aggressively scaled (1.4nm
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::57f2720785844fe9d4fe865933c74aa5
https://doi.org/10.1109/led.2006.876312
https://doi.org/10.1109/led.2006.876312
Autor:
Navakanta Bhat, Kingsuk Maitra
Publikováno v:
IEEE Transactions on Electron Devices. 51:409-414
In this paper, we perform rigorous mixed-mode simulations on two-stage inverter circuit and sample-hold circuits, representative of digital, and analog applications, respectively. The impact of gate-source/drain overlap length on circuit performance
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8f01e391dd0144b011e339881100cbbe
https://doi.org/10.1109/ted.2003.822347
https://doi.org/10.1109/ted.2003.822347
Autor:
R. J. Miller, J. Faltermeier, Pranita Kulkarni, Bruce B. Doris, Kingsuk Maitra, D. McHerron, N R Klymko, E Leobundung, H. Adhikari, Huiming Bu, Chun-Chen Yeh, Katherine L. Saenger, Vamsi Paruchuri, J. O'Neil, Veeraraghavan S. Basker, Ali Khakifirooz, Theodorus E. Standaert, Hemanth Jagannathan
Publikováno v:
IEEE Electron Device Letters. 32:713-715
Strained-silicon-on-insulator (SSOI) undoped-body high-κ /metal-gate n-channel fin-shaped field-effect transistors (nFinFETs) at scaled gate lengths and pitches (i.e.,LGATE ~ 25 nm and a contacted gate pitch of 130 nm) were fabricated using a gate-f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1a1ed78e22846ada1bac7635a99cdc8e
https://doi.org/10.1109/led.2011.2126556
https://doi.org/10.1109/led.2011.2126556
Autor:
S. Chen, Rune Hartung Jensen, Brian Keith Langendorf, Tung Thanh Nguyen, Ranjit Gannamani, Raj N. Master, Julia Purtell, N. Liu, A. Marathe, M. Mccormack, Kingsuk Maitra, S. Dixit
Publikováno v:
2014 IEEE International Reliability Physics Symposium.
The SOFR model is modified for SOCs in consumer electronics applications such as game consoles for advanced logic technology nodes (~2X nm). Using a representative voltage/temperature dataset from XBOX ONE SOC operation, a quantitative measure of “
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6acec7e9a1538a6542518a4d541f08a5
https://doi.org/10.1109/irps.2014.6860647
https://doi.org/10.1109/irps.2014.6860647
Autor:
Andreas Kerber, Frank Yeh, Robert J. Miller, Chung-Hsun Lin, Huiming Bu, Veeraraghavan S. Basker, Kingsuk Maitra, Pranita Kulkarni, Sujata Paul, Hemanth Jagannathan
Publikováno v:
IEEE Electron Device Letters. 31:650-652
A methodology based on the transistor body effect is used to monitor inversion oxide thicknesses (Tinv's) in high-κ/metal-gate undoped ultrathin-body short-channel SOI FINFETs. The extracted Tinv's are benchmarked to independent capacitance-voltage
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::482c063490da6bf066a387154553aee6
https://doi.org/10.1109/led.2010.2049634
https://doi.org/10.1109/led.2010.2049634
A simulation study to evaluate the feasibility of midgap workfunction metal gates in 25 nm bulk CMOS
Autor:
Kingsuk Maitra, Veena Misra
Publikováno v:
IEEE Electron Device Letters. 24:707-709
The performance of 25 nm metallurgical channel length bulk MOSFETs with midgap workfunction metal gates has been compared with conventional polysilicon gates and bandedge workfunction metal gates. Device design using pocket halo implants was implemen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1562231f208a17401f6ee977c1f6bdab
https://doi.org/10.1109/led.2003.819267
https://doi.org/10.1109/led.2003.819267