Zobrazeno 1 - 10
of 24
pro vyhledávání: '"King-Ho Tam"'
Autor:
Chao-Chieh Li, Sheng-Yao Yang, Sandeep Kumar Goel, Shu-Chun Yang, Tze-Chiang Huang, Kenny Hsieh, Chien-Chun Tsai, King-Ho Tam, Wen-Hung Huang, Ching-Fang Chen, Stefan Rusu, Yu-Chi Chen, Frank Lee, Mei Wong, Chi-Wei Hu, Chin-Ming Fu, Mu-Shan Lin
Publikováno v:
IEEE Journal of Solid-State Circuits. 55:956-966
We present a dual-chiplet interposer-based system-in-package (SiP) octo-core processor using Chip-on-Wafer-on-Substrate (CoWoS) technology. Each of the two identical chiplets is implemented in 7-nm CMOS with 15 metal layers and has four Arm Cortex-A7
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d58192107c16e8f0be44a991828295f7
https://doi.org/10.1109/jssc.2019.2960207
https://doi.org/10.1109/jssc.2019.2960207
Autor:
Jack Hu, Mei Wong, Tom Chen, Chien-Chun Tsai, Wen-Hung Huang, Mu-Shan Lin, Sandeep Kumar Goel, Chin-Ming Fu, Chao-Chieh Li, Shu-Chun Yang, Stefan Rusu, Frank Lee, Cheng-Hsiang Hsieh, Sheng-Yao Yang, Tze-Chiang Huang, King-Ho Tam, Yu-Chi Chen
Publikováno v:
VLSI Circuits
A dual-chiplet Chip-on-Wafer-on-Substrate (CoWoS®) was implemented in 7nm 15M process. Each SoC chiplet has four Arm® Cortex®-A72 processors operating at 4GHz. The on-die interconnect mesh bus operates above 4GHz at 2mm distance. The inter-chiplet
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f931d1b867c7f86e87c8c5a39ef7c318
https://doi.org/10.23919/vlsic.2019.8778161
https://doi.org/10.23919/vlsic.2019.8778161
Autor:
Ke-Ying Su, Te-Yu Liu, Chung-Kai Lin, King-Ho Tam, Min-Chie Jeng, Cheng Tai-Yu, Kevin Chen, Cheng Hsiao, Jun-Fu Huang, Ke-Wei Su, Kuo-Pei Lu, Joshua Sun, Chun Cheng, Katherine Chiang
Publikováno v:
2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
A comprehensive variation model is critical to achieve both competitive design and manufacturing yield in advanced technologies. Conventionally, as long as FEOL (front end of line) statistical model is appropriate, BEOL (back end of line) variations
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9a23615575616050edd1fbdf7803ccb
https://doi.org/10.1109/sispad.2016.7605208
https://doi.org/10.1109/sispad.2016.7605208
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:1498-1502
This paper presents the first in-depth study on dual-Vdd buffer insertion for power minimization under delay constraint. Compared with delay-optimal single Vdd buffer insertion, the dual- Vdd buffer insertion reduces power by 16%. Such power reductio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e659321ce5381232c89f2bb997bf7bc
https://doi.org/10.1109/tcad.2008.925784
https://doi.org/10.1109/tcad.2008.925784
Publikováno v:
ISPD
This paper studies the impacts of Chemical Mechanical Polishing (CMP)-induced systematic variation and random channel length (Leff) variation of transistors on interconnect design. We first construct a table look-up based interconnect RC parasitic mo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ffb863e18725b1a9ab09f88228533247
https://doi.org/10.1109/tcad.2007.8361579
https://doi.org/10.1109/tcad.2007.8361579
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 26:845-857
This paper presents extensions of the dynamic-programming (DP) framework to consider buffer insertion and wire-sizing under effects of process variation. We study the effectiveness of this approach to reduce timing impact caused by chemical-mechanica
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f447567b1c738a0538ef907b06264cc1
https://doi.org/10.1109/tcad.2006.884869
https://doi.org/10.1109/tcad.2006.884869
Publikováno v:
DAC
For nanometer design, conventional timing analysis may generate over-optimistic results on criticality-dependent paths. A late arrival time at the data input of a flip-flop lengthens the propagation delay from the clock pin to the data output of this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::823724ced547b68ff7fb6c3aa48ebcba
https://doi.org/10.1145/2744769.2744812
https://doi.org/10.1145/2744769.2744812
Autor:
Nitesh Katta, Ken Chung-Hsing Wang, Homer Yen-Hung Lin, Meng-Kai Hsu, King Ho Tam, Keny Tzu-Hen Lin
Publikováno v:
2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
Newest manufacturing technologies with feature sizes smaller than 20nm and FinFET devices have favored more restrictive design rules for manufacturability while suffering from electrical limitations of electromigration (EM) and variability. Designers
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5388b2a8e9b9ef2142e7225980d94b37
https://doi.org/10.1109/iccad.2014.7001408
https://doi.org/10.1109/iccad.2014.7001408
Publikováno v:
SLIP
This paper presents fast algorithms for power-optimal interconnect synthesis based on interconnect prediction and sampling considering dual Vdd buffers. We present three pruning techniques including interconnect prediction based pruning (pre-buffer s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4a6b72030ba0af67a6d1c580bcc2097
https://doi.org/10.1145/1231956.1231976
https://doi.org/10.1145/1231956.1231976
Publikováno v:
Design and Process Integration for Microelectronic Manufacturing III.
Dummy fill insertion in Chemical-mechanical Planarization (CMP) can change the coupling and total capacitance of interconnect. Moreover, dishing and erosion phenomena change interconnect cross-sections and hence significantly affect interconnect resi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c4c4bc59ca4cdfa38e0ae9206831a5c
https://doi.org/10.1117/12.605222
https://doi.org/10.1117/12.605222