Zobrazeno 1 - 4
of 4
pro vyhledávání: '"King C. Yen"'
Autor:
King C. Yen, Aparna Ramachandran, Timothy P. Johnson, Yongning Sheng, Jason M. Hart, Daisy Jian, Rakesh Mehta, Yuefei Ge, Dawei Huang, Lance Kwong, Hoyeol Cho, Zuxu Qin, Changku Hwang, Jinuk Luke Shin, Umesh Gajanan Nawathe, Robert P. Masleid, Venkat Krishnaswamy, Georgios Konstadinidis, Hari Sathianathan, Gregory Gruber, Sebastian Turullols
Publikováno v:
ISSCC
The 3.6 GHz SPARC T5 processor is Oracle's next generation CMT SoC processor implemented in TSMC's 28 nm process with 1.5 billion transistors. Significant performance improvements were made by doubling the previous generations number of cores to 16 a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9a65bf3aeb8482508a1512e9ba2b864
https://doi.org/10.1109/jssc.2013.2284648
https://doi.org/10.1109/jssc.2013.2284648
Autor:
King C. Yen, Amit Kumar, David J. Greenhill, Umesh Gajanan Nawathe, Mahmud Hassan, Aparna Ramachandran
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:6-20
The second in the Niagara series of processors (Niagara2) from Sun Microsystems is based on the power-efficient chip multi-threading (CMT) architecture optimized for Space, Watts (Power), and Performance (SWaP) [SWap Rating = Performance/(Space * Pow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d30300acb31dce6ba2b28f6781cd06c8
https://doi.org/10.1109/jssc.2007.910967
https://doi.org/10.1109/jssc.2007.910967
Autor:
Venkat Krishnaswamy, Yifan YangGong, Daniel Woo, Changku Huang, Sebastian Turullols, King C. Yen, Kalon Holdbrook, Jinuk Luke Shin
Publikováno v:
A-SSCC
In order to minimize the impact of on-chip Ldi/dt noise on power and performance, Oracle's SPARC M6 processor features an Asymmetric Frequency Locked Loop (AFLL) that dynamically adjusts chip frequency. It achieves 15% improved noise immunity by reac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45c21a1474cdf719ced2477b249a1157
https://doi.org/10.1109/asscc.2014.7008938
https://doi.org/10.1109/asscc.2014.7008938
Autor:
Bharath Upputuri, Amit Kumar, L. Warriner, David J. Greenhill, King C. Yen, Mahmud Hassan, U.M. Nawathe, H. Park
Publikováno v:
ISSCC
The 8-core 64-thread 64b power-efficient 2nd-generation Niagara SPARC SoC has 4MB L2 cache with one times8 PCI-Express, two 10G Ethernet (XAUI), and 8 FBDIMM ports. The on-chip SerDes provide greater than 1Tb/s bandwidth. The 500M transistor chip wit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24bca89923cfdb54d8bb601b4afbb4cd
https://doi.org/10.1109/isscc.2007.373611
https://doi.org/10.1109/isscc.2007.373611