Zobrazeno 1 - 10
of 80
pro vyhledávání: '"Kimmo Kuusilinna"'
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 19:466-477
This paper introduces a configurable motion estimation architecture for a wide range of fast block-matching algorithms (BMAs). Contemporary motion estimation architectures are either too rigid for multiple BMAs or the flexibility in them is implement
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87d03d72733dd313560139ed53937a23
https://doi.org/10.1109/tcsvt.2009.2014012
https://doi.org/10.1109/tcsvt.2009.2014012
Publikováno v:
IEEE Transactions on Circuits and Systems for Video Technology. 18:538-543
This paper proposes an efficient parallel memory system for algorithms applied in fixed and variable block-size motion estimation (VBSME). The proposed system is implemented by a novel combination of two parallel memory architectures. The distributio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::988687ad500495945dce8037bf91a2bd
https://doi.org/10.1109/tcsvt.2008.918273
https://doi.org/10.1109/tcsvt.2008.918273
Publikováno v:
Microprocessors and Microsystems. 31:283-292
Image downscaling is necessary in multiresolution video streaming and when a camera captures larger resolution frames than required. This paper presents an implementation of a downscaler capable of real-time scaling of color video. The scaler can be
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97480e77619812d2e71a37c983d7d097
https://doi.org/10.1016/j.micpro.2006.09.003
https://doi.org/10.1016/j.micpro.2006.09.003
Autor:
Vesa Lahtinen, Jouni Riihimäki, Erno Salminen, Tero Kangas, Timo Hämäläinen, Kimmo Kuusilinna
Publikováno v:
Journal of Systems Architecture. 53:477-488
The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f29b6ec7703ff21a7c6961800c2ab36e
https://doi.org/10.1016/j.sysarc.2006.11.006
https://doi.org/10.1016/j.sysarc.2006.11.006
Autor:
Tero Kangas, Kimmo Kuusilinna, Vesa Lahtinen, Erno Salminen, Jouni Riihimäki, Timo Hämäläinen
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 43:185-205
This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2262060b6c88c72b65b5718d2444f7f7
https://doi.org/10.1007/s11265-006-7270-6
https://doi.org/10.1007/s11265-006-7270-6
Publikováno v:
Journal of VLSI signal processing systems for signal, image and video technology. 44:79-95
Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, progr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::effdc5117efb598e1a8c282f4dc0ae45
https://doi.org/10.1007/s11265-006-5918-x
https://doi.org/10.1007/s11265-006-5918-x
Publikováno v:
Journal of Systems Architecture. 47:1089-1115
This paper presents a novel parallel memory architecture for multimedia computers. Applying a configurable or programmable addressing circuitry capable of parallel memory accesses, the memory management of multimedia applications can be enhanced. Nec
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d98e75246c83390cc81119afc0c15506
https://doi.org/10.1016/s1383-7621(02)00059-0
https://doi.org/10.1016/s1383-7621(02)00059-0
Publikováno v:
IEE Proceedings - Computers and Digital Techniques. 148:23-30
Finite state machine (FSM) optimisation has usually been studied through state assignment, state vector encoding, and combinational logic optimisation. Such details should not be consequential in behavioural descriptions. On the other hand, describin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c82216a334223f4bc1e778f1c4062582
https://doi.org/10.1049/ip-cdt:20010210
https://doi.org/10.1049/ip-cdt:20010210
Publikováno v:
Microprocessors and Microsystems. 23:459-469
This paper gives a hands-on example of how low-level optimization of the VHSIC Hardware Description Language (VHDL) code is extremely difficult within a contemporary Field Programmable Gate Array (FPGA) design flow. However, low-level optimization ca
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4d692cc0592780cd1780771642082da9
https://doi.org/10.1016/s0141-9331(99)00062-9
https://doi.org/10.1016/s0141-9331(99)00062-9
Publikováno v:
Microprocessors and Microsystems. 22:373-388
This paper presents the design and implementation of a field programmable gate array (FPGA)-based PCI bus interface for a general purpose parallel neurocomputer, which is hosted by a personal computer. The basic background of the PCI bus and a detail
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce5f17790f83e938ef2dda467c6ec4a3
https://doi.org/10.1016/s0141-9331(98)00090-8
https://doi.org/10.1016/s0141-9331(98)00090-8