Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Kim-yong Goh"'
Publikováno v:
2022 IEEE 24th Electronics Packaging Technology Conference (EPTC).
Publikováno v:
2017 IEEE 19th Electronics Packaging Technology Conference (EPTC).
This paper provides a comprehensive study done experimentally and numerically to understand which are the key factors effecting block warpage and propose a practical modeling method for BOM selection based on the design for manufacturability approach
Autor:
Wingshenq Wong, Yiyi Ma, Kim-yong Goh, Tito Verano, Raquel Fundan, Xueren Zhang, Loic Pierre Louis Renard
Publikováno v:
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
As microelectronics is moving towards miniaturization, function integration and cost reduction, the device itself is becoming smaller while keeping same or even more functions. Silicon die with area less than 2×2 mm2 is common. This poses challenges
Publikováno v:
2014 IEEE 16th Electronics Packaging Technology Conference (EPTC).
Drop test is transient and dynamic in nature. Therefore, explicit solvers such as ANSYS/LS-DYNA and ABQUAS Explicit are employed extensively for the free fall analysis [1-3]. To avoid complexity in modeling contact event, a simplified Input-G method
Publikováno v:
2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counter
Publikováno v:
2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
System-in-Package (SiP) which combines different chips and technologies into a single package is a viable solution to meet the rigorous requirements for today's mixed signal system integration. As the level of integration increases, challenges relate
Publikováno v:
2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).
Thermo-mechanical reliability is one of the major concerns for electronic packages, especially for power packages operating in extremely harsh environment. As the trends towards high density and function integration, advanced power device becomes mor
Publikováno v:
2012 35th IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT).
The associated significant loss with passive devices on silicon substrate is generally believed to be responsible for the presence of low quality factors, making it a poor candidate for the design of efficient output matching networks. STMicroelectro
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
In this paper, we will compare Cu wire and Au wire behavior during pull test and package reliability test through thermo-mechanical simulation. Relationship between wire pull test and package reliability test, i.e. thermal cycling, is also evaluated
Publikováno v:
2009 11th Electronics Packaging Technology Conference.
Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard Ball Grid Array Packages and leadframe based packages because of smaller size, better electrical and thermal p