Zobrazeno 1 - 10
of 86
pro vyhledávání: '"Kia Bazargan"'
Publikováno v:
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84a2ff1cbac5310101909aa2d126e85c
https://doi.org/10.1145/3543622.3573181
https://doi.org/10.1145/3543622.3573181
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 15:1-25
Multipliers are used in virtually all Digital Signal Processing (DSP) applications such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50ee945b559b7563f11103e99ad9006f
https://doi.org/10.1145/3494570
https://doi.org/10.1145/3494570
Publikováno v:
ACM Transactions on Reconfigurable Technology and Systems. 14:1-25
The binary number representation has dominated digital logic for decades due to its compact storage requirements. An alternative representation is the unary number system: We use N bits, from which the first M are 1 and the rest are 0 to represent th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d8edc7f6fc451f4b39faaf9a242d9a79
https://doi.org/10.1145/3418464
https://doi.org/10.1145/3418464
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:1821-1832
Stochastic computing (SC) in recent years has been defined as a digital computation approach that operates on streams of random bits that represent probability values. SC can perform complex tasks with much smaller hardware footprints compared with c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2df5bee87168949649138b288e84d7fb
https://doi.org/10.1109/tvlsi.2020.2984731
https://doi.org/10.1109/tvlsi.2020.2984731
Autor:
S. Rasoul Faraji, Kia Bazargan
Publikováno v:
ICCAD
Multipliers are the basic building blocks of modern DSP systems and contribute significantly to their overall performance. In many DSP systems, using truncated multipliers instead of full precision multipliers can keep the accuracy at a desirable lev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c279e70d05397637bac284dae12cde35
https://doi.org/10.1145/3400302.3415700
https://doi.org/10.1145/3400302.3415700
Publikováno v:
ISCAS
Convolutional layers account for 90% of the total computational power of Convolutional Neural Networks (CNNs). Field programmable gate arrays (FPGAs) have shown great potential for accelerating inference tasks in CNNs. However, it is harder for FPGA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d921596a41ec4455c8bd80e7d907c490
https://doi.org/10.1109/iscas45731.2020.9180836
https://doi.org/10.1109/iscas45731.2020.9180836
Publikováno v:
ISCAS
Near-sensor convolution engines have many applications in Internet-of-Things. Pulsed unary processing has been recently proposed for high-performance and energy-efficient processing of data using simple digital logic. In this work, we propose a low-c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c25f08062eda133d548900375b783258
https://doi.org/10.1109/iscas45731.2020.9181248
https://doi.org/10.1109/iscas45731.2020.9181248
Publikováno v:
2018 ASEE Annual Conference & Exposition Proceedings.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::96360349fef3a655a0c5fe6094054efa
https://doi.org/10.18260/1-2--30571
https://doi.org/10.18260/1-2--30571
Publikováno v:
FCCM
Multipliers are used in virtually all Digital Signal Processing (DSP) applications, such as image and video processing. Multiplier efficiency has a direct impact on the overall performance of such applications, especially when real-time processing is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4da75490b3bfbf0a3979a57cc11eae46
https://doi.org/10.1109/fccm48280.2020.00022
https://doi.org/10.1109/fccm48280.2020.00022
Publikováno v:
Hardware Architectures for Deep Learning ISBN: 9781785617683
In this chapter, we proposed a low-cost and energy -efficient design for hardware implementation of CNNs. LD deterministic bit -streams and simple standard AND gates are used to perform fast and accurate multiplication operations in the first layer o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa6ff9d5e093460d5381c5378f21641e
https://doi.org/10.1049/pbcs055e_ch4
https://doi.org/10.1049/pbcs055e_ch4
