Zobrazeno 1 - 10
of 46
pro vyhledávání: '"Ki-Heung Park"'
Autor:
Jae-Hyun Kang, Aliaa Kabeel, Namjae Kim, Sangah Lee, Wael ElManhawy, Marwah Shafee, Sangwoo Jung, Asmaa Rabie, Kareem Madkour, Ahmed ElGhoroury, Seung Weon Paek, Joe Kwan, Ki-Heung Park, Jiwon Oh
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIII.
As the typical litho hotspot detection runtime continue to increase with sub-10nm technology node due to increasing design and process complexity, many DFM techniques are exploring new methods that can expedite some of their advanced verification pro
Autor:
Kyoung-Il Na, Jong-Ho Lee, Sorin Cristoloveanu, Maryline Bawedin, Ki-Heung Park, Jung-Hee Lee, Young-Ho Bae
Publikováno v:
Solid-State Electronics. 67:17-22
We demonstrate a new fully depleted (FD) double-gate (DG) MSDRAM cell, which features SONOS type storage node at the back-gate (control-gate). This single-transistor cell, based on the meta-stable dip (MSD) hysteresis effect, can also be operated in
Publikováno v:
Solid-State Electronics
We propose a double-gate (DG) 1T-DRAM cell combining SONOS type storage node on the back-gate (control-gate) for nonvolatile memory function. The cell sensing margin and retention time characteristics were systematically examined in terms of control-
Publikováno v:
IEEE Transactions on Electron Devices. 57:614-619
We proposed for the first time a new double-gate 1T-DRAM cell to be applicable to sub-80-nm DRAM technology that has a silicon-oxide-nitride-oxide-silicon type storage node on the back gate (control gate) for nonvolatile memory (NVM) functionality. A
Publikováno v:
Microelectronic Engineering. 86:2045-2048
Pulsed plasma-immersion ion implantation (PIII) or Pulsed PLAsma Doping (P^2LAD) is known as a cost effective solution for ultra shallow junction formation due to its capability to implant doping species at ultra-low energies (0.05-5keV), the advanta
Publikováno v:
Journal of the Korean Physical Society. 53:3411-3415
We propose a cell structure with non-overlap source/drain (S/D) (or without S/D) for a NAND ash memory, which utilizes the fringing eld from control gates. In this work, a guideline for the cell device design is suggested through extensive device sim
Autor:
Ki-Heung Park, Jong-Ho Lee
Publikováno v:
Japanese Journal of Applied Physics. 47:5365-5368
We present a comparative study of p+/n+ gate modified saddle metal oxide semiconductor field effect transistors (MOSFETs) and p+/n+ gate bulk fin field effect transistors (FinFETs) that have been proposed for sub-40 nm dynamic random access memory (D
Publikováno v:
IEEE Transactions on Nanotechnology. 7:427-433
In this paper, design considerations for the n+/p+/n+ gate bulk FinFET in sub-50-nm technology nodes is extensively studied through 3D device simulation. For the comparison of electrical characteristics of n+/p+/n+ gate bulk FinFET, the electrical ch
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 8:156-163
We proposed a new p?/n? gate locallyseparated- channel (LSC) bulk FinFET which has vertically formed oxide region in the center of fin body, and device characteristics were optimized and compared with that of normal channel (NC) FinFET. Key device ch
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 7:76-81
Threshold voltage (V th ) modeling of doublegate (DG) MOSFETs was performed, for the first time, by considering barrier lowering in the short channel devices. As the gate length of DG MOSFETs scales down, the overlapped charge-sharing length (x h ) i