Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Ki-Chul Chun"'
Publikováno v:
IEEE Access, Vol 9, Pp 33487-33497 (2021)
As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased. As a result, DRAM vendors perform post package inspections to provide fa
Externí odkaz:
https://doaj.org/article/14bfe40df87d40c1a5cb37454d13b862
Autor:
Sung-Gi Ahn, Yong-ki Kim, Ryu Ye-Sin, Kyomin Sohn, Ki-Chul Chun, Dong Hak Shin, Byung-Kyu Ho, Jae-Won Park, Ji-Hye Kim, Chi Sung Oh, Byoung Mo Moon, Jae-Seung Jeong, Nam Sung Kim, S.J. Ahn, Jun Jin Kong, Seong-Jin Cho, Jun Gyu Lee, Jung-Bae Lee, So-Young Kim, Young Yong Byun, Seouk-Kyu Choi, Jae-Hoon Lee, Woo Seunghan, Soo-Young Kim, Min-Sang Park, Beomyong Kil
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:199-211
Circuit and design techniques are presented for enhancing the performance and reliability of a 3-D-stacked high bandwidth memory-2 extension (HBM2E). A data-bus window extension technique is implemented to cope with reduced clock cycle time ranging f
Publikováno v:
IEEE Access, Vol 9, Pp 33487-33497 (2021)
As the technology node of the dynamic random-access memory (DRAM) continues to decrease below the 10-nm-class, bit-cell failures due to the external environments have increased. As a result, DRAM vendors perform post package inspections to provide fa
Autor:
Jin-Guk Kim, Kijun Lee, Junyong Noh, Seungseob Lee, Jung-Bae Lee, Seung-Duk Baek, Jungyu Lee, Sin-Ho Kim, Soo-Young Kim, Hye-In Choi, Ki-Chul Chun, Beomyong Kil, Sanguhn Cha, So-Young Kim, Jae-Won Park, Ryu Ye-Sin, Jun Jin Kong, Dong-Hak Shin, Byung-Kyu Ho, Hyuk-Jun Kwon, Baekmin Lim, Park Yong-Sik, Seouk-Kyu Choi, Chi-Sung Oh, Kyomin Sohn, Myungkyu Lee, Kwang-Il Park, Young-Yong Byun, Jae-Wook Lee, Bo-Tak Lim, Seong-Jin Cho, Jong-Pil Son, Yong-ki Kim, Nam Sung Kim, S.J. Ahn
Publikováno v:
ISSCC
Rapidly evolving artificial intelligence (Al) technology, such as deep learning, has been successfully deployed in various applications: such as image recognition, health care, and autonomous driving. Such rapid evolution and successful deployment of
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1861-1871
Embedded nonvolatile memory (eNVM) is considered to be a critical building block in future system-on-chip and microprocessor systems. Various eNVM technologies have been explored for high-density applications including dual-poly embedded flash (eflas
A Write-Back-Free 2T1D Embedded DRAM With Local Voltage Sensing and a Dual-Row-Access Low Power Mode
Publikováno v:
CICC
A gain cell embedded DRAM (eDRAM) in a 65 nm LP process achieves a 1.0 GHz random read access frequency by eliminating the write-back operation. The read bitline swing of the 2T1D cell is improved by employing short local bitlines connected to local
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:1302-1314
Embedded flash memory implemented using standard I/O devices can open doors to new applications and system capabilities, as it can serve as a secure on-chip non-volatile storage for VLSI chips built in standard logic processes. For example, it is ind
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:598-610
This paper explores the scalability of in-plane and perpendicular MTJ based STT-MRAMs from 65 nm to 8 nm while taking into consideration realistic variability effects. We focus on the read and write performances of a STT-MRAM based cache rather than
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:2517-2526
A truly logic-compatible gain cell eDRAM macro with no boosted supplies is presented. A 2T1C gain cell implemented only with regular thin oxide devices consists of an asymmetric 2T cell and a coupling PMOS capacitor. The PMOS capacitor ensures proper
Publikováno v:
IEEE Journal of Solid-State Circuits. 47:547-559
Circuit techniques for enhancing the retention time and random cycle of logic-compatible embedded DRAMs (eDRAMs) are presented. An asymmetric 2T gain cell utilizes the gate and junction leakages of a PMOS write device to maintain a high data `1' volt