Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Ki Chang Kwean"'
Autor:
Sang-Sic Yoon, Ki-Chang Kwean, Byong-Tae Chung, Mun-Phil Park, Yong-ki Kim, Sun-Suk Yang, Kyung-hoon Kim, Dae-Han Kwon
Publikováno v:
ESSCIRC
A 1 Gb density, 5.2 Gbps/s/pin data rate GDDR5 SDRAM was developed using 66 nm DRAM process. It uses traditional Core architecture, 8-bit pre-fetch with 16-banks, but the clocking and interface topology are fully changed for operating more than 4 Gbp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a97f77ab748e85ee07a0aa3928e479f
https://doi.org/10.1109/esscirc.2008.4681825
https://doi.org/10.1109/esscirc.2008.4681825
Autor:
Young-Kyoung Choi, Won-Joo Yun, Ki-Chang Kwean, Won Jun Choi, Seung-Wook Kwack, Young-Jung Choi, Shin-Deok Kang, Sang-hoon Shin, Joong-Sik Kih, Hyong-Uk Moon, Hyun-woo Lee, Kwan-Weon Kim, Hyang-Hwa Choi, Hyeng-Ouk Lee, Nak-Kyu Park, Jung-Woo Lee, Young Ju Kim, Dong Uk Lee, Jin-Hong Ahn, Ye-Seok Yang
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
A new low power, low cost and high performance register-controlled digital delay locked loop with wide locking range is presented. The DLL has dual loops with single replica block, duty cycle correction enhance controller (DCCEC), smart power down co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6ce5ff40096b319a115e06fb9c94ea05
https://doi.org/10.1109/asscc.2006.357916
https://doi.org/10.1109/asscc.2006.357916
Autor:
Joong-Sik Kih, Jin-Hong Ahn, Won-Joo Yun, Young-Jung Choi, Seung-Wook Kwack, Sin-Deok Kang, Hyung-Wook Moon, Dong Uk Lee, Ki-Chang Kwean, Hyun-woo Lee, Kwan-Weon Kim
Publikováno v:
2005 IEEE Asian Solid-State Circuits Conference.
A new low power high performance register-controlled digital delay locked loop (LPRCDLL) is presented. The circuit has fine delay compensation ability, fast delay compensation according to external voltage variation, and inherent duty correction. The
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::efc8e632b8558ab60e6dcf4eb35eb38b
https://doi.org/10.1109/asscc.2005.251750
https://doi.org/10.1109/asscc.2005.251750
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL.
Autor:
Dong Uk Lee, Hyun Woo Lee, Ki Chang Kwean, Young Kyoung Choi, Hyong Uk Moon, Seung Wook Kwack, Shin Deok Kang, Kwan Weon Kim, Yong Ju Kim, Young Jung Choi, Moran, P., Jin Hong Ahn, Joong Sik Kih
Publikováno v:
2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers; 2006, p547-556, 10p
Autor:
Won-Joo Yun, Hyun-Woo Lee, Young-Ju Kim, Won-Jun Choi, Sang-Hoon Shin, Hyang-Hwa Choi, Hyeng-Ouk Lee, Shin-Deok Kang, Hyong-Uk Moon, Seung-Wook Kwack, Dong-Uk Lee, Jung-Woo Lee, Young-Kyoung Choi, Nak-Kyu Park, Ki-Chang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Joong-Sik Kih, Ye-Seok Yang
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference; 2006, p323-326, 4p
Autor:
Hyun-Woo Lee, Won-Joo Yun, Sin-Deok Kang, Hyung-Wook Moon, Seung-Wook Kwack, Dong-Uk Lee, Ki-Chang Kwean, Kwan-Weon Kim, Young-Jung Choi, Jin-Hong Ahn, Joong-Sik Kih
Publikováno v:
2005 IEEE Asian Solid-State Circuits Conference; 2005, p401-404, 4p