Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Khoa Minh Nguyen"'
Publikováno v:
Energies, Vol 16, Iss 9, p 3792 (2023)
Nowadays, wind power generation has become vital thanks to its advantages in cost, ecological friendliness, enormousness, and sustainability. However, the erratic and intermittent nature of this energy poses significant operational and management dif
Externí odkaz:
https://doaj.org/article/328e7f1a243c42c2afafbdbe4ed3ee59
Autor:
Tho Alang1,2 alangtho@hcmiu.edu.vn, Khoa Minh Nguyen1,2 nmkhoa.69@gmail.com
Publikováno v:
International Journal of Electronic Commerce Studies. 2022, Vol. 13 Issue 2, p177-195. 19p.
Autor:
Phu Cong Nguyen, Dang-Khoa Le-Nguyen, Huu Phuc To, Quoc Dung Phan, Khoa-Minh Nguyen-Huu, Bao Anh Nguyen, Le Nam Pham
Publikováno v:
2021 International Symposium on Electrical and Electronics Engineering (ISEE).
This paper proposes a decentralized capacitor voltage control strategy for the flying capacitor multilevel inverter (FC-MLI) in combination with the decentralized self-aligned phase-shifted pulse width modulation (PWM) (self-aligned carriers) method.
Autor:
Kuan-Yueh Shen, Syed Feruz Syed Farooq, Khoa Minh Nguyen, Yongping Fan, Wang Qi, Nasser A. Kurd, Mark L. Neidengard, Amr Elshazly
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 65:2109-2117
This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to
Publikováno v:
ISLPED
In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture impo
Autor:
Khoa Minh Nguyen, Muhammad Faisal, Hyung Seok Kim, Satoshi Suzuki, Paolo Madoglio, Amr Fahim, Yorgos Palaskas, Zhichao Zhang, Hongtao Xu, Tan Yulin, Luis Cuellar, Stefano Pellerano, Jianyong Xie, Yanjie Wang, Kailash Chandrashekar, Parmoon Seddighrad, Ashoke Ravi, Divya Shree Vemparala, Thomas A. Tetzlaff, Brent Carlton, William Yee Li, Vaibhav Vaidya
Publikováno v:
ISSCC
To benefit from Moore's law and minimize form-factor and active power consumption, digital-rich SoCs should be integrated in the most advanced technology node. If the transceiver is integrated in a different technology node, multi-chip solutions are
Akademický článek
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Autor:
R. Yavatkar, Chang-Tsung Fu, Taehwan Kim, Hasnain Lakdawala, Ajay Balankutty, Chun Lee, Satoshi Suzuki, Hyung-Jin Lee, Rahul Limaye, P. Vandervoorn, Brent Carlton, Erkan Alpman, S. Ramamurthy, Jad B. Rizk, Durgesh Srivastava, Krishnamurthy Soumyanath, Duster Jon Sweat, Stefano Pellerano, Tan Yulin, C.-H. Jan, Marian Verhelst, Mark A. Schaecher, Ashoke Ravi, Satish Venkatesan, Khoa Minh Nguyen, Hyung Seok Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 48:91-103
An t 86 standard operating system compliant System-on-Chip (SoC) with a dual core ATOM processor and a custom interconnect fabric to enable modular design is presented. The 32 nm SoC includes integrated PCI-e Gen 2, DDR3, legacy I/O, voltage regulato
Autor:
Nasser A. Kurd, Wang Qi, Yongping Fan, Kuan-Yueh James Shen, Syed Feruz Syed Farooq, Khoa Minh Nguyen, Amr Elshazly
Publikováno v:
ISSCC
With recent advancements in SoC integration, modern SoC architectures can employ more than 20 PLLs [1]. To address SoC clocking needs with an ever reducing power budget, a deep sub-mW to low-mW PLL having a FoM between −226dB and −234dB from 0.8G
Akademický článek
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