Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Khawar Sarfraz"'
Autor:
Danfeng Xu, Haikun Jia, Tairan Zhu, Xiaolong Liu, Yang Zhang, Man Pio Lam, C. Conroy, Quan Pan, Ming Kwan, Ka Fai Mak, Chi Fai Tang, Wing Hong Szeto, Zichuan Cheng, Paul Lai, Emily Yim Lee Au, Khawar Sarfraz, Yu Kou, L. Moser, Kai Keung Chan, Tze Yin Cheung
Publikováno v:
ISSCC
The proliferation of hyperscale data centers, as well as edge and 5G infrastructure build-outs, requires SerDes running at different rates, over different insertion losses, and in different environments. This work presents a scalable ADC/DSP-based tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e9a12ac0f53aac946983e59f095cbe84
https://doi.org/10.1109/isscc42613.2021.9366063
https://doi.org/10.1109/isscc42613.2021.9366063
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:2215-2220
This paper presents a sub-threshold SRAM, which eliminates bitline (BL) leakage-induced read failures. The proposed architecture clamps the current ratio between differential BLs to a fixed value, thus permitting reliable ultra-low-voltage read-out.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6cff2496fd44655552964eb1334ca75
https://doi.org/10.1109/jssc.2017.2707392
https://doi.org/10.1109/jssc.2017.2707392
Autor:
Khawar Sarfraz, Mansun Chan
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 64:360-372
This paper presents a 44.2-mW 3.2-GHz 3-port register file (RF) that demonstrates measured operation from 1.2 V down to 0.4 V. The 32-entry× 32-bit/word 2-read/1-write RF is fabricated in TSMC 65-nm low-power low threshold voltage (low-V t ) CMOS pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dfb17386e8b6a24893f62767c226fcb2
https://doi.org/10.1109/tcsi.2016.2613282
https://doi.org/10.1109/tcsi.2016.2613282
Autor:
Khawar Sarfraz, Mansun Chan
Publikováno v:
Integration. 55:12-21
An area-efficient 4-port register file with low power consumption is presented for mobile application processors. Area efficiency at array level is achieved with a novel compact bitcell that supports single-ended one-sided read operations using the d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bc3d78f345dec9552e421b8e51196005
https://doi.org/10.1016/j.vlsi.2016.02.008
https://doi.org/10.1016/j.vlsi.2016.02.008
Autor:
Khawar Sarfraz, Mansun Chan
Publikováno v:
MWSCAS
A voltage-scalable bitline leakage current suppression technique with zero wake-up delay penalty is proposed to minimize the standby power consumption of low threshold voltage dynamic register files (RFs). Leakage currents via the pull-down paths of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::543b3357fabeae15fe9bfcd0b0084484
https://doi.org/10.1109/mwscas.2016.7869951
https://doi.org/10.1109/mwscas.2016.7869951
Autor:
Mansun Chan, Khawar Sarfraz
Publikováno v:
ASICON
This paper discusses key circuit-level challenges associated with the design of multi-port register file (RF) memories. Notable solutions proposed to address these challenges are presented. Some of the challenges and opportunities associated with nov
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d9ac435c51779badb8338693086caa4a
https://doi.org/10.1109/asicon.2015.7516882
https://doi.org/10.1109/asicon.2015.7516882
Autor:
Mansun Chan, Khawar Sarfraz
Publikováno v:
ESSCIRC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::062a55e37608c524f249101ec7937ec4
https://doi.org/10.1109/esscirc.2015.7313894
https://doi.org/10.1109/esscirc.2015.7313894
Autor:
Mansun Chan, Khawar Sarfraz
Publikováno v:
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
An area-efficient 4-port register file is presented for real-time microprocessors. Bitcell area efficiency is achieved with one-sided read operations and single-ended write operations together with an additional higher voltage source for write operat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81b51ca3999f75087e8155b81fc32ac9
https://doi.org/10.1109/edssc.2015.7285085
https://doi.org/10.1109/edssc.2015.7285085
Autor:
Khawar Sarfraz, Mansun Chan
Publikováno v:
2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC).
In this paper, two write ability enhancement techniques are presented for the L1 data cache on next-generation IBM POWERTM processors. Write ability is improved by 15.1% at 1.2V with V DD lowering technique for a dual-ported 6T bitcell with a beta ra
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c28f39b2c8b93957c01916d94310312d
https://doi.org/10.1109/edssc.2015.7285192
https://doi.org/10.1109/edssc.2015.7285192