Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Kevin W. Gorman"'
Publikováno v:
IEEE Design & Test. 33:31-37
With the growing number and speed of embedded memories, testing for delay defects in the logic surrounding RAMs is becoming increasingly important. This article introduces DFT techniques for testing the transition faults at the memory functional boun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1a88e39080b520b8c50e7e84c89abd3
https://doi.org/10.1109/mdat.2016.2590981
https://doi.org/10.1109/mdat.2016.2590981
Publikováno v:
IEEE Design & Test of Computers. 28:14-21
As power and density requirements for embedded memories grow, products ranging from mobile applications to high-performance microprocessors are increasingly looking toward eDRAM as an alternative to SRAM. This article describes the state of the art i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a3520d70ef74af04e481aceebd146915
https://doi.org/10.1109/mdt.2011.2
https://doi.org/10.1109/mdt.2011.2
Publikováno v:
ITC
Delay faults on the inputs and outputs of memories embedded in an integrated circuit are difficult to cover efficiently in manufacturing test. A complicated approach, separate from standard digital logic tests or memory built-in self-test, is needed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b0153714487eb385bd864ac5990977f9
https://doi.org/10.1109/test.2015.7342411
https://doi.org/10.1109/test.2015.7342411
Autor:
Darren L. Anand, S. Sliva, Jeffrey H. Dreibelbis, Dale E. Pontius, Michael R. Nelms, Erik A. Nelson, S. Burns, Kevin W. Gorman, Adrian J. Paparelli, John E. Barth, G. Pomichter, John A. Fifield
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:213-222
This work describes a 500-MHz compiled eDRAM macro offered in a 90-nm logic-based process. The macro architecture is optimized for high bandwidth while enabling compilation in bank and data-word dimensions. A direct write scheme simultaneously improv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::01a70e212ab54fca80057305bcaab0c8
https://doi.org/10.1109/jssc.2004.838001
https://doi.org/10.1109/jssc.2004.838001
Autor:
J. Paparelli, John A. Fifield, Dale E. Pontius, Michael A. Roberge, S. Sliva, Kevin W. Gorman, Jeffrey H. Dreibelbis, Darren L. Anand, J. Covino, G. Pomichter, Mark D. Jacunski
Publikováno v:
CICC
An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum2 cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh all
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::14541abf360e7654127a45f03b2a7e54
https://doi.org/10.1109/cicc.2007.4405849
https://doi.org/10.1109/cicc.2007.4405849
Autor:
G. Pomichter, Michael A. Roberge, Adrian J. Paparelli, W.R. Corbin, Kevin W. Gorman, S. Sliva
Publikováno v:
ITC
This paper discusses the unique challenges in constructing an architecture and methodology for testing a 1 GHz 65 nm Embedded DRAM in an ASIC environment. The concepts of multiplication of both test commands and test clock frequency are discussed in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9056ccd8b6c746370827b96fd4de12a4
https://doi.org/10.1109/test.2007.4437566
https://doi.org/10.1109/test.2007.4437566
Publikováno v:
CICC
This work presents architectures and methods necessary for providing efficient and thorough test of high bandwidth embedded memories using low speed ATE. Details are also provided on the techniques used to minimize test related silicon area and test
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7e0f80ed1d9a77a89bda1240d19296e8
https://doi.org/10.1109/cicc.2006.320820
https://doi.org/10.1109/cicc.2006.320820
Publikováno v:
VTS
A circuit has been developed to accurately generate embedded memory fail maps utilizing At-Speed test clocks generated from low-speed automated test equipment (ATE). The circuit provides a simple interface to communicate between the BIST and ATE for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::75333f7b73fe1fc248018bac20168c7e
https://doi.org/10.1109/vtest.2004.1299230
https://doi.org/10.1109/vtest.2004.1299230