Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Kevin McStay"'
Autor:
Michal Rakowski, Kate McLean, Asli Sahin, Bo Peng, Brendan Harris, Karen Nummy, Javier Ayala, Andy Stricker, Ken Giewont, Abdelsalam Aboketaf, Louis Medina, John Pellerin, Zoey Sowinski, Jacob Ajey Poovannummoottil, Ted Letavic, Kevin McStay, Yusheng Bian, Thomas Houghton, Dave Riggs, Anthony Yu, Crystal Hedges, Colleen Meagher
Publikováno v:
OFC
Scopus-Elsevier
Scopus-Elsevier
GLOBALFOUNDRIES’ monolithic 45nm CMOS-Silicon Photonics 300mm high-volume manufacturing platform based on 45nm RF technology node, and optimized for high performance and low power short-reach optical interconnects for on-chip and chip-to-chip appli
Publikováno v:
IEEE Transactions on Electron Devices. 62:1357-1359
The introduction of FinFET architecture was expected to alleviate the issue of mismatch compared with planar technology, given the lower doping levels required. However, several authors have reported better mismatch results for planar technology sugg
Autor:
E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao
Publikováno v:
2014 IEEE International Electron Devices Meeting.
We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat
Publikováno v:
ECS Transactions. 52:57-59
We report that uniaxial strain in silicon FETs results in a significant modification of subthreshold and near threshold characteristics. We show that modulation of the effective mobility in the region of VTH via uniaxial strain is very nearly proport
Autor:
Rajeev Malik, Rishikesh Krishnan, Sunfei Fang, Bernhard Wunder, Kevin McStay, Yanli Zhang, Sadanand V. Deshpande, Douglas Daley, Herbert L. Ho, Sneha Gupta, Paul C. Parries, Balaji Jayaraman, Sungjae Lee, Puneet Goyal, John E. Barth, Scott R. Stiffler, Paul D. Agnello, Subramanian S. Iyer
Publikováno v:
ICICDT
In this paper, we present a systematic performance study and modeling of on-chip deep trench (DT) decoupling capacitors for high-performance SOI microprocessors. Based on system-level simulations, it is shown that the DT decoupling capacitors (decap)
Autor:
James H. Stathis, Andreas Kerber, R. Divakaruni, Yue Hu, Hemanth Jagannathan, Dae-Gyu Park, Siddarth A. Krishnan, Richard Carter, Deleep R. Nair, Yun-Yu Wang, Ricardo A. Donaton, William K. Henson, Shahab Siddiqui, Ernest Y. Wu, Murshed M. Chowdhury, Kathy Barla, Huiming Bu, Mukesh Khare, Rohit Pal, J.-P. Han, Matthew W. Stoker, S. Saroop, Sufi Zafar, Michael P. Chudzik, Eduard A. Cartier, X. Chen, Jin Cai, Vamsi Paruchuri, Eric C. Harley, Myung-Hee Na, Dimitris P. Ioannou, Ryosuke Iijima, Min Dai, Kevin McStay, Takashi Ando, Joseph F. Shepard, J. Schaeffer, J-H Lee, Naim Moumen, P. Montanini, Lisa F. Edge, Paul D. Agnello, Shreesh Narasimha, Srikanth Samavedam, Dechao Guo, Unoh Kwon, Dominic J. Schepis, Yue Liang, Martin Ostermayr, S. Inumiya, Thomas A. Wallner, B. Greene, H. Yamasaki, D.P. Prakash, Jaeger Daniel, Stephen W. Bedell, M. Hargrove, Michael A. Gribelyuk, Gauri Karve, Y. Lee, Vijay Narayanan, S. Uchimura, Martin M. Frank
Publikováno v:
2011 International Electron Devices Meeting.
Band-gap engineering using SiGe channels to reduce the threshold voltage (V TH ) in p-channel MOSFETs has enabled a simplified gate-first high-к/metal gate (HKMG) CMOS integration flow. Integrating Silicon-Germanium channels (cSiGe) on silicon wafer
Autor:
Herbert L. Ho, Jinping Liu, Paul C. Parries, Norman Robson, Jing Li, Puneet Goyal, S.S. Iyer, Ming Yin, Babar A. Khan, Zhengwen Li, Paul D. Agnello, K. V. Hawkins, Sunfei Fang, T. Weaver, Scott R. Stiffler, Kevin McStay, Rishikesh Krishnan, W. Davies, R. Takalkar, T. Kirihata, Sami Rosenblatt, S. Galis, A. Blauberg, Shreesh Narasimha, Michael P. Chudzik, Amanda L. Tessier, William K. Henson, W. Kong, Edward P. Maciejewski, Alberto Cestero, Nauman Zafar Butt, Joseph Ervin, S. Gupta, Jeyaraj Antony Johnson, S. Rombawa, Sungjae Lee, J. Barth, Ying Zhang
Publikováno v:
2010 International Electron Devices Meeting.
We present industry's smallest eDRAM cell and the densest embedded memory integrated into the highest performance 32nm High-K Metal Gate (HKMG) SOI based logic technology. The cell is aggressively scaled at 58% (vs. 45nm) and features the key innovat
Autor:
Russell H. Arndt, Ashima B. Chakravarti, Anthony G. Domenicucci, Amanda L. Tessier, Jinping Liu, Sunfei Fang, Kevin McStay, Zhengwen Li, Randolph F. Knarr, S. Lee, Joseph F. Shepard, Herbert L. Ho, A. Arya, R. Venigalla, W. Davies, R. Takalkar, Rishikesh Krishnan, Paul C. Parries, B. Morgenfeld, Xin Li, S. Gupta, Michael P. Chudzik, Scott R. Stiffler, Puneet Goyal, Babar A. Khan, Sadanand V. Deshpande, J. Dadson, Scott D. Allen
Publikováno v:
2010 IEEE International SOI Conference (SOI).
In this paper, we describe the unique scaling challenges, critical sources of variation, and the potential trench leakage mechanisms of 32nm trench capacitors that utilize high-к/metal electrode materials. This is the first eDRAM technology that has
Autor:
S.S. Iyer, Ravi M. Todi, Rajeev Malik, Erik A. Nelson, Rishikesh Krishnan, Sunfei Fang, Byeong Y. Kim, R. Takalkar, D. Anand, Oh-Jung Kwon, Michael P. Chudzik, Nauman Zafar Butt, Scott R. Stiffler, Herbert L. Ho, Joseph Ervin, Siddarth A. Krishnan, Babar A. Khan, Alberto Cestero, Gregory G. Freeman, Geng Wang, Karen A. Nummy, J. Sim, Amanda L. Tessier, Jin Liu, W. Kong, Paul C. Parries, Kevin McStay
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
A high performance embedded DRAM with deep trench capacitor and high performance SOI logic has been deployed in 45nm and 32nm technology nodes. Following a yield ramp of the sub-2ns latency 45nm technology, we present, for the first time, a 32nm eDRA
Autor:
S.H. Ku, Myung-Hee Na, L. R. Logan, J. Friedrich, Richard Q. Williams, F. Clougherty, Gregory G. Freeman, Brian J. Greene, Noah Zamdmer, B. Dufrene, D. Slisher, Emmanuel F. Crabbe, E.J. Nowak, Q. Liang, Dureseti Chidambarrao, Scott K. Springer, Kevin McStay, Judith H. McCullen
Publikováno v:
2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).
Recently, 65 nm technology-based microprocessors have been introduced into high-end products such as games processors and high- performance servers [1]. As technology development in the modern-day relies more and more on non-traditional performance-