Zobrazeno 1 - 10
of 60
pro vyhledávání: '"Kevin D. Lucas"'
Publikováno v:
Microelectronic Engineering. :87-90
With the development of modern optical lithography techniques enabling dimensions less than the wavelength of the source being used to be printed, the use of simulation is becoming very widespread. It is primarily used to predict the requirements and
Autor:
Bernard J. Roman, Robert John Socha, Kurt E. Wampler, Patrick K. Montgomery, Kevin D. Lucas, Douglas Van Den Broeke, Christopher J. Progler, Lloyd C. Litt, J. Fung Chen, Michael E. Hathorn, Wei Wu, Willard E. Conley, Thomas Laidig, Bryan S. Kasprowicz
Publikováno v:
SPIE Proceedings.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/- 9nm 1 . Defectivity levels must also be below one failure
Autor:
Bernard J. Roman, Willard E. Conley, Emilien Robert, Richard D. Peters, Michael E. Hathorn, Christopher J. Progler, Martin Chaplin, Erika Schaefer, Lloyd C. Litt, Colita Parker, J. Fung Chen, Jan-Pieter Kuijten, Stephan van de Goor, Kurt E. Wampler, Arjan Verhappen, Thomas Laidig, Robert John Socha, Wei Wu, Philippe Thony, Douglas Van Den Broeke, Bryan S. Kasprowicz, Kevin D. Lucas
Publikováno v:
SPIE Proceedings.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investi
Autor:
Kyle Patterson, Jerome Belledent, Christophe Couderc, Yorick Trouiller, Frank Sundermann, Yves Rody, Kevin D. Lucas, Sergei V. Postnikov
Publikováno v:
SPIE Proceedings.
Mask error factor (MEEF) is a commonly used metric in lithography. This parameter gives a good indication of the impact of intra-mask CD variation on the wafer. Unfortunately, MEEF is useless to anticipate the CD variation on the wafer induced by Mas
Autor:
Kurt E. Wampler, Fung Chen, Philippe Thony, Emilien Robert, Jan-Pieter Kuijten, Thomas Laidig, Bernard J. Roman, Bryan S. Kasprowicz, Kevin D. Lucas, Erika Schaefer, Stephan van de Goor, Christopher J. Progler, Martin Chaplin, Lloyd C. Litt, Will Conley, Colita Parker, Douglas Van Den Broeke, Richard D. Peters, Wei Wu, Robert John Socha, Arjan Verhappen
Publikováno v:
SPIE Proceedings.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been i
Autor:
Robert John Socha, Bernard J. Roman, Christopher J. Progler, Bryan S. Kasprowicz, Patrick K. Montgomery, Arjan Verhappen, Kevin D. Lucas, Wil Pijnenburg, Wei Wu, Kurt E. Wampler, Will Conley, Pat Cook, Erika Schaefer, Lloyd C. Litt, Jan-Pieter Kuijten
Publikováno v:
SPIE Proceedings.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors
Publikováno v:
SPIE Proceedings.
The cost of developing and deploying optical proximity correction (OPC) technology has become a non-negligible part of the total lithography cost of ownership (CoO). In this paper, we present our efforts to reduce costs associated with OPC in the dev
Autor:
Kirk J. Strozewski, Robert Boone, Olivier Toublan, Karl Wimmer, Kevin D. Lucas, Bill Wilkinson, Ruiqi Tian, Jonathan L. Cobb, Chi-Min Yuan, Jason Porter
Publikováno v:
SPIE Proceedings.
The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithogra
Autor:
Johannes van Wingerden, Lloyd C. Litt, Michael Cangemi, Geert Vandenberghe, Patrick Montgomery, Eric L. Fanucchi, Bryan S. Kasprowicz, Kevin D. Lucas, Vincent Wiaux, Will Conley, Darren Taylor
Publikováno v:
SPIE Proceedings.
The minimum gate pitch for the 65nm device node will push 193nm lithography toward k1 ~ 0.35 with NA = 0.85. Previous work has analyzed the challenges expected for this generation. However, in the simplest terms, optical lithography for the 65nm node
Publikováno v:
SPIE Proceedings.
Conventional lithography techniques have been losing their ability to easily support continuous shrinking of feature sizes, especially when the pattern half-pitch is