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Publikováno v:
ACM Transactions on Design Automation of Electronic Systems. 11:490-500
A unique LVS (layout-versus-schematic) methodology has been developed for the verification of a four-core microprocessor with multiple power domains using a triple-well 90-nm CMOS technology. The chip is migrated from its previous generation that is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92bb83c9b2c543a17cd0e841226fa27a
https://doi.org/10.1145/1142155.1142166
https://doi.org/10.1145/1142155.1142166
