Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Ketul B. Sutaria"'
Autor:
Ketul B. Sutaria, Minki Cho, Anisur Rahman, Jihan Standfest, Rahul Sharma, Swaroop Namalapuri, Shiv Gupta, Bahar Ajdari, Ricardo Ascazubi, Balkaran Gill
Publikováno v:
2022 IEEE International Reliability Physics Symposium (IRPS).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::70d3105948317c4f1ce21d2f3aed9929
https://doi.org/10.1109/irps48227.2022.9764598
https://doi.org/10.1109/irps48227.2022.9764598
Autor:
Jeffery Hicks, Swaroop Kumar Namalapuri, S. Ramey, Jihan Standfest, A. H. Davoody, Balkaran Gill, P Supriya, T. Mutyala, Ketul B. Sutaria, Inanc Meric
Publikováno v:
IRPS
Circuit reliability is a significant concern in scaled technologies. Physical aging models derived by DC stress on discrete devices are accurate to an extent, but can be further improved by evaluating the behaviour of simple circuits such as ring osc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92e1d3e8db04ba67afcdc9d97dfabbfe
https://doi.org/10.1109/irps45951.2020.9128347
https://doi.org/10.1109/irps45951.2020.9128347
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 25:2248-2257
Random numbers play a vital role in cryptography, where they are used to generate keys, nonce, one-time pads, and initialization vectors for symmetric encryption. The quality of random number generator (RNG) has significant implications on vulnerabil
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47c8dc27ec46ac76a86175f705a5aaad
https://doi.org/10.1109/tvlsi.2017.2687762
https://doi.org/10.1109/tvlsi.2017.2687762
Autor:
Lei Jiang, Mark Armstrong, K. W. Park, Inanc Meric, J. Standfest, C. D. Landon, Sell Bernhard, S. Liu, Ketul B. Sutaria, K. Phoa, David Young, C.-Y. Su, J. Wan, L. Paulson, S. A. Kumar, S. Ramey
Publikováno v:
IRPS
This paper describes the transistor reliability of Intel's 22FFL FinFET technology, which includes an extensive variety of device offerings to enable high performance and low power design options. Detailed evaluations of BTI, TDDB, self-heating, and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e92475c423b4613c1c5bbd9612327d3
https://doi.org/10.1109/irps.2018.8353652
https://doi.org/10.1109/irps.2018.8353652
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 15:384-393
Aging mechanisms such as Bias Temperature Instability (BTI) and Channel Hot Carrier (CHC) are key limiting factors of circuit lifetime in CMOS design. Threshold voltage shift of a device due to degradation is usually a gradual process, only causing m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4db273dfed834ce8a235f80f0e0d26f0
https://doi.org/10.1109/tdmr.2015.2456893
https://doi.org/10.1109/tdmr.2015.2456893
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 14:607-615
Design for reliability is an increasingly important design step at advanced technology nodes. Aggressive scaling has brought forth reliability issues, such as negative bias temperature instability (NBTI). The aging process due to NBTI exhibits a sign
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b874411425c7f856111c129f488eaa8a
https://doi.org/10.1109/tdmr.2014.2308140
https://doi.org/10.1109/tdmr.2014.2308140
Autor:
Michael Bajura, Michael Fritze, Jyothi Velamala, Ketul B. Sutaria, Yu Cao, Ivan Sanchez Esqueda, J. R. Ahlbin, Mike Shuo-Wei Chen
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 33:8-23
Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2627a313647bc193cdb734d6705e5654
https://doi.org/10.1109/tcad.2013.2289874
https://doi.org/10.1109/tcad.2013.2289874
Autor:
Ketul B. Sutaria, Hiromitsu Awano, Hirofumi Shimizu, Gilson Wirth, Yu Cao, Takashi Sato, Jyothi Velamala
Publikováno v:
IEEE Transactions on Electron Devices. 60:3645-3654
The aging process due to negative bias temperature instability (NBTI) is a key limiting factor of circuit lifetimes in CMOS design. Recent NBTI data exhibits an excessive amount of randomness and fast recovery, which are difficult to be handled by co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cb677a2da2fe1116a01cd9825b18d50d
https://doi.org/10.1109/ted.2013.2281986
https://doi.org/10.1109/ted.2013.2281986
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 13:340-349
With CMOS technology scaling, design for reliability has become an important step in the design cycle and increased the need for efficient and accurate aging simulation methods during the design stage. NBTI-induced delay shifts in logic paths are asy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::885cb8854d9f0e75e60ab391fa606199
https://doi.org/10.1109/tdmr.2012.2235441
https://doi.org/10.1109/tdmr.2012.2235441
Autor:
Ru Huang, Runsheng Wang, Xixiang Feng, Pengpeng Ren, Yu Cao, Abinash Mohanty, Ketul B. Sutaria
Publikováno v:
IRPS
Aging due to bias-temperature-instability (BTI) is the dominant cause of functional failure in large scale logic circuits. Power efficient techniques such as clock gating or dynamic voltage scaling exacerbate the problem of asymmetric aging. Traditio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51165375f8caab11a0acc382308e7c3f
https://doi.org/10.1109/irps.2015.7112785
https://doi.org/10.1109/irps.2015.7112785