Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Ketan Padalia"'
Publikováno v:
FPGA
In this paper, we describe the application of two parallelization strategies to the Quartus II FPGA placer. The first uses a pipelining approach and achieves speedups of 1.3x on two processing cores. The second uses a parallel moves approach and achi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4ed5559bd46e1ce66b8b8b6fce6b684a
https://doi.org/10.1145/1344671.1344676
https://doi.org/10.1145/1344671.1344676
Autor:
Mark Bourgeault, David Galloway, Gregg William Baeckler, Elias Ahmed, Andy L. Lee, David Lewis, Boris Ratchev, Sandy Marquardt, Christopher F. Lane, Richard G. Cliff, Srinivas T. Reddy, Bruce B. Pedersen, Michael D. Hutton, Jay Schleicher, Paul Leventis, Giles Powell, Cameron McClintock, Kevin Stevens, David Cashman, Jonathan Rose, Ketan Padalia, Vaughn Betz, Richard Yuan
Publikováno v:
FPGA
This paper describes the Altera Stratix II™ logic and routing architecture. This architecture features a novel adaptive logic module (ALM) that is based on a 6-LUT, but can be partitioned into two smaller LUTs to efficiently implement circuits cont
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9738e2d073e8960b557efba21f30ba7d
https://doi.org/10.1145/1046192.1046195
https://doi.org/10.1145/1046192.1046195
Autor:
Andy L. Lee, David Lewis, Boris Ratchev, Rahul Saini, Sinan Kaptanoglu, Jay Schleicher, Ketan Padalia, Gregg William Baeckler, Bruce B. Pedersen, Michael D. Hutton, Henry Kim, Richard Yuan, Mark Bourgeault
Publikováno v:
Field Programmable Logic and Application ISBN: 9783540229896
FPL
FPL
This paper proposes a new adaptable FPGA logic element based on fracturable 6-LUTs, which fundamentally alters the longstanding belief that a 4-LUT is the most efficient area/delay tradeoff. We will describe theory and benchmarking results showing a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::09ec0ab9a1ce8489895ee7fda52ba1f1
https://doi.org/10.1007/978-3-540-30117-2_16
https://doi.org/10.1007/978-3-540-30117-2_16
Publikováno v:
ACM Transactions on Embedded Computing Systems; Jan2015, Vol. 14 Issue 1, p18:1-18:26, 26p
Autor:
Gutierrez, Fernando, Corral-Briones, Graciela, Morero, Damian, Goette, Teodoro, Ramos, Facundo
Publikováno v:
2012 VIII Southern Conference on Programmable Logic; 1/ 1/2012, p1-6, 6p
Publikováno v:
Proceedings of the 16th International ACM/SIGDA Symposium: Field Programmable Gate Arrays; 2/24/2008, p14-23, 10p
Publikováno v:
Proceedings of the 2005 ACM/SIGDA 13th International Symposium: Field-programmable Gate Arrays; 2/20/2005, p215-226, 12p
Autor:
Lewis, David, Ahmed, Elias, Baeckler, Gregg, Betz, Vaughn, Bourgeault, Mark, Cashman, David, Galloway, David, Hutton, Mike, Lane, Chris, Lee, Andy, Leventis, Paul, Marquardt, Sandy, McClintock, Cameron, Padalia, Ketan, Pedersen, Bruce, Powell, Giles, Ratchev, Boris, Reddy, Srinivas, Schleicher, Jay, Stevens, Kevin
Publikováno v:
Proceedings of the 2005 ACM/SIGDA 13th International Symposium: Field-programmable Gate Arrays; 2/20/2005, p14-20, 7p
Publikováno v:
Proceedings of the 2003 ACM/SIGDA Eleventh International Symposium: Field Programmable Gate Arrays; 2/23/2003, p164-172, 9p
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