Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Kenway Tam"'
Autor:
J. Kaku, J. Hart, S. Vishwanthaiah, D. Murata, G. Yee, Yet-Ping Pai, Raymond A. Heald, S. Nguyen, Kathirgamar Aingaran, Song Kim, Chin Kim, E. You, D. Greenley, G. Lauterbach, J. Grinberg, H. McIntyre, Roger Y. Lo, G. Gouldsberry, K. Shin, Wen-Jay Hsu, Chaim Amir, T. Horel, A. Mehta, J. Wu, F. Klass, P. Dixit, M. Ang, S. Patel, H. Kwan, M. Boland, Kenway Tam
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1526-1538
This quad-issue processor achieves 1-GHz operation through improved dynamic circuit techniques in critical paths and a more extensive on-chip memory system which scales in both bandwidth and latency. Critical logic paths use domino, delayed clocked d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::193ee259cf3f3bc2c4e86ab5eeb7d519
https://doi.org/10.1109/4.881196
https://doi.org/10.1109/4.881196
Autor:
Jinuk Luke Shin, David J. Greenhill, Kenway Tam, Ana Sonia Leon, Francis Schumacher, Dawei Huang, Allan Strong, Alan Smith, Bruce Petrick, Changku Hwang, Timothy Johnson, Hongping Li, Ha Pham
Publikováno v:
ISSCC
This next generation of Chip Multithreaded (CMT) SPARC SoC processor, code named Rainbow Falls, doubles on-chip thread count over its predecessor the UltraSparc T2+. The chip offers high levels of integration and scalability with twice the number of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::443e01e44955fd737aaeaa4caf15b0df
https://doi.org/10.1109/isscc.2010.5434030
https://doi.org/10.1109/isscc.2010.5434030
Autor:
R. Heald, K. Aingaran, C. Amir, M. Ang, M. Boland, A. Das, P. Dixit, G. Gouldsberry, J. Hart, T. Horel, null Wen-Jay Hsu, J. Kaku, null Chin Kim, null Song Kim, F. Klass, null Hang Kwan, null Roger Lo, H. McIntyre, A. Mehta, D. Murata, S. Nguyen, null Yet-Ping Pai, S. Patel, K. Shin, null Kenway Tam, S. Vishwanthaiah, J. Wu, null Gin Yee, null Hong You
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
This 3rd-generation, superscalar processor, implementing the SPARC V9 64 b architecture, improves performance over previous processors by improvements in the on-chip memory system and circuit designs enhancing the speed of critical paths beyond the p
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5240f052f01c9f359a03e8f7a2f3852c
https://doi.org/10.1109/isscc.2000.839838
https://doi.org/10.1109/isscc.2000.839838