Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Kenneth J. Reyer"'
Autor:
Alberto Cestero, Gregory J. Fredeman, Toshiaki Kirihata, Janakiraman Viraraghavan, Abraham Mathews, Babar A. Khan, Subramanian S. Iyer, Daniel J. Rainey, Chris Paone, Donald W. Plass, Thomas R. Miller, Michael A. Sperling, Herbert L. Ho, Norbert Arnold, Elizabeth L. Gerhard, Rajesh R. Tummuru, Dinesh Kannambadi, Michael Whalen, Steven Burns, Kenneth J. Reyer, Dongho Lee, Thomas J. Knips
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:230-239
A 1.1 Mb embedded DRAM macro (eDRAM), for next-generation IBM SOI processors, employs 14 nm FinFET logic technology with $\hbox{0.0174}~\mu\hbox{m}^{2}$ deep-trench capacitor cell. A Gated-feedback sense amplifier enables a high voltage gain of a pow
Autor:
Michael A. Sperling, Donald W. Plass, Thomas R. Miller, Elizabeth L. Gerhard, Dongho Lee, Dinesh Kannambadi, Thomas J. Knips, Michael Whalen, Kenneth J. Reyer, Chris Paone, Daniel J. Rainey, S. Burns, Gregory J. Fredeman, Abraham Mathews
Publikováno v:
ISSCC
IBM introduced trench capacitor eDRAM into its high performance microprocessors beginning with 45nm and Power 7 [1] to provide a higher density cache without chip crossings. Whereas the 45 and 32nm designs employ a micro sense amplifier [2] and three
Autor:
James W. Dawson, Donald W. Plass, Thomas J. Knips, John Davis, Paul A. Bunce, D. Malone, P. Pritzlaff, Kenneth J. Reyer, J. DellaPietro
Publikováno v:
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
This paper describes the design and results of SRAM experiments from a prototype test chip in IBM's .18 /spl mu/m 7 level metal copper technology. Results and approaches for assuring product applications at 1 GHz across wide process ranges will be di