Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Keng-Jan Hsiao"'
Autor:
Keng-Jan Hsiao, 蕭耕然
96
The delay-locked loop(DLL) is widely used in many aspects, such as the generation of multiphase clocks or clock generator. In this dissertation, a fully integrated multiplying DLL and a distributed DLL are covered. A general impedance convert
The delay-locked loop(DLL) is widely used in many aspects, such as the generation of multiphase clocks or clock generator. In this dissertation, a fully integrated multiplying DLL and a distributed DLL are covered. A general impedance convert
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/64038407974126033393
Autor:
Keng-Jan Hsiao, 蕭耕然
93
The FCC has approved an unlicensed usage of spectrum from 3.2 GHz to 10.5 GHz called “ultra wide band (UWB)”. There are two proposed standards that are MBOA and DS respectively for this application. The MBOA-UWB system utilizes MB-OFDM te
The FCC has approved an unlicensed usage of spectrum from 3.2 GHz to 10.5 GHz called “ultra wide band (UWB)”. There are two proposed standards that are MBOA and DS respectively for this application. The MBOA-UWB system utilizes MB-OFDM te
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/18862796445396046818
Autor:
Chien-Ming Chen, Jia-Feng Jiang, Cheng-Chung Yang, Keng-Jan Hsiao, Shon-Hang Wen, Cheng-Yu Chien, Chieh-Hung Chen
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:2241-2251
This paper presents a load-adaptive Class-G headphone amplifier to improve the power efficiency for different headphone impedances. For an impedance value, the amplifier utilizes two techniques, voltage rails selection and Class-G switching activity
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4477ec400645a90e2794b758255e3d1c
https://doi.org/10.1109/jssc.2016.2581802
https://doi.org/10.1109/jssc.2016.2581802
Autor:
Keng-Jan Hsiao, Tai-Cheng Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2478-2487
A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-tim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66c88740faac015ee8e067e457d7ef26
https://doi.org/10.1109/jssc.2009.2024804
https://doi.org/10.1109/jssc.2009.2024804
Autor:
Jia-Feng Jiang, Cheng-Yu Chien, Keng-Jan Hsiao, Chieh-Hung Chen, Chien-Ming Chen, Shon-Hang Wen, Cheng-Chung Yang
Publikováno v:
A-SSCC
A Class-G headphone amplifier for hi-fi audio playback with high immunity to supply disturbance and Class-G switching noise is presented that achieves 130dB PSRR at 217Hz and higher than 100dB PSRR up to 20kHz. In addition, a Class-G amplifier with l
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::662fd67d543cba61f93da4be2f38f726
https://doi.org/10.1109/asscc.2015.7387442
https://doi.org/10.1109/asscc.2015.7387442
Autor:
Tai-Cheng Lee, Keng-Jan Hsiao
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:1245-1252
A delay-locked loop (DLL)-based frequency synthesizer is designed for the ultrawideband (UWB) Mode-1 system. This frequency synthesizer with 528-MHz input reference frequency achieves less than 9.5-ns settling time by utilizing wide loop bandwidth an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::916e4756ef8cb3ccafa24c2a9b23e890
https://doi.org/10.1109/jssc.2006.874353
https://doi.org/10.1109/jssc.2006.874353
Autor:
Keng-Jan Hsiao
Publikováno v:
ISSCC
A 32.768kHz crystal (XTAL) with its oscillation circuit is widely adopted for the generation of the real-time keeping and system-standby clock. Both functions are universally demanded by various systems such as cellular phones, smart wearable devices
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::49bf426e21aba7621889d72096ae017d
https://doi.org/10.1109/isscc.2014.6757442
https://doi.org/10.1109/isscc.2014.6757442
Publikováno v:
2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).
As the data rate increases above Gb/s, the design of a clock and data recovery (CDR) circuit becomes a great challenge. A 3.125-Gb/s CDR is proposed to shorten the frequency acquisition time by employing a wide-linear-range frequency detector. Fabric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::659aa17cd84c8b99103e69a5133d6794
https://doi.org/10.1109/vdat.2008.4542427
https://doi.org/10.1109/vdat.2008.4542427
Autor:
Tai-Cheng Lee, Keng-Jan Hsiao
Publikováno v:
ISSCC
A low-jitter distributed DLL for multiple-phase clock generation is proposed. The distributed DLL monitors the phase difference for each output clock and the reference clock. This distributed DLL is fabricated in a 90 nm CMOS process and consumes 15
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6194c79af7ed80251618ab109cf42829
https://doi.org/10.1109/isscc.2008.4523283
https://doi.org/10.1109/isscc.2008.4523283
Autor:
Keng-Jan Hsiao, Tai-Cheng Lee
Publikováno v:
2007 IEEE Symposium on VLSI Circuits.
A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39ff9b6016c559d171a00411a54dab64
https://doi.org/10.1109/vlsic.2007.4342730
https://doi.org/10.1109/vlsic.2007.4342730