Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Keng Hwa Teo"'
Autor:
Ser Choong Chong, Sanming Hu, Keng Hwa Teo, Eva Wai, Minkyu Je, Rui Li, Cheng Jin, Ming Chinq Jong, Patrick Guo-Qiang Lo, Hongyu Li
Publikováno v:
IEEE Transactions on Electron Devices. 61:2584-2587
This brief proposes an electrical method using simple resistor chain in parallel to quickly locate open circuits in a 3-D chip. This method is theoretically analyzed using the equivalent circuit, and experimentally validated by a 3-D integrated circu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::12b4cf82f34c922e30d881c521a89e8c
https://doi.org/10.1109/ted.2014.2321453
https://doi.org/10.1109/ted.2014.2321453
Autor:
Minkyu Je, Jinglin Shi, Yong Han, Mohammad Madihian, Xiaowu Zhang, Yong Zhong Xiong, Hongyu Li, Yen Yi Germaine Hoe, Dan Zhao, Keng Hwa Teo, Jin He, Sanming Hu
Publikováno v:
IEEE Transactions on Electron Devices. 60:1282-1287
This brief proposes a guard ring using through-silicon vias (TSVs) to isolate thermal coupling in a 3-D integrated circuit (3-D IC). To verify this idea, simulation and measurement are carried out. A ring oscillator (RO) is implemented in a 65-nm CMO
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e3677bd613cc08f4eee33127272aa966
https://doi.org/10.1109/ted.2013.2243452
https://doi.org/10.1109/ted.2013.2243452
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 2:944-955
Through-silicon via (TSV) technology has been widely investigated recently for 3-D electronic packaging integration. Reducing TSV wafer warpage is one of the most challenging concerns for successfully subsequent processes. In this paper, a wafer-leve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a49f22fd5725e9c4e4e2f32a71a671ec
https://doi.org/10.1109/tcpmt.2012.2192732
https://doi.org/10.1109/tcpmt.2012.2192732
Autor:
Keng Hwa Teo, S. Gao, Yen Chen Yeo, Hongyu Li, Guan Kian Lau, Jaesik Lee, Justin Seetoh, Vincent Lee
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 1:1988-1995
The effects of temporary bonding processes on thin wafer handling were investigated. Backside dielectric curing process was found to be a critical process for the void formation in the thin wafer handling which was confirmed by scanning acoustic micr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::957704b0f5c4b1689a935c034121f36e
https://doi.org/10.1109/tcpmt.2011.2162435
https://doi.org/10.1109/tcpmt.2011.2162435
Publikováno v:
IEEE Electron Device Letters. 34:18-20
Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orien
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2e6dd94241fec2ecb6bc29e264b0a3cc
https://doi.org/10.1109/led.2012.2228158
https://doi.org/10.1109/led.2012.2228158
Autor:
Srinivasa Rao Vempati, Eva Wai Leong Ching, Jie Li Aw, Ser Choong Chong, Hongyu Li, Keng Hwa Teo, Daniel Ismael Cereno
Publikováno v:
2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013).
Industry is adopting three-dimensional integration of Cu-low k Chip with micro-solder bumps by stacking process to increase the functionality and performance of the device. Cu/low k is known to be very fragile and required special packaging process t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d987ef0654ebba5a1f3b4b852f503ab4
https://doi.org/10.1109/eptc.2013.6745722
https://doi.org/10.1109/eptc.2013.6745722
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
3D Through-silicon via (TSV) has been acknowledged as one of the future chip design technologies. In this paper, via last after Back End Of Line (BEOL) and before bonding, CMOS wafer with 18 layers of multilayer dielectric dry etching prior to deep s
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e34b330a806daafcde6b71bc32bb16e6
https://doi.org/10.1109/eptc.2011.6184491
https://doi.org/10.1109/eptc.2011.6184491
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
Industry is moving towards having module with multiple functions and capabilities in order to satisfy consumer demands. Miniaturized the package will allowed more components to pack inside the electronic gadget. A low z-foot print of the package is o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c83e67b9c51f39ce9cbd6f9462e37da
https://doi.org/10.1109/eptc.2011.6184396
https://doi.org/10.1109/eptc.2011.6184396
Publikováno v:
2011 IEEE 13th Electronics Packaging Technology Conference.
RDL process becomes more and more important with through Si interposer (TSI) application in 3D packaging. RDL line/space needs to be shrinking with the increasing of device density. We had been developed low temperature (LT) damascene process for the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b47a2ad459024f028475bcdba8db3ec5
https://doi.org/10.1109/eptc.2011.6184442
https://doi.org/10.1109/eptc.2011.6184442
Autor:
S. Gao, Justin Seetoh, Keng Hwa Teo, Jaesik Lee, Yen Chen Yeo, Serene Thew, Hongyu Li, Vincent Lee
Publikováno v:
2011 IEEE 61st Electronic Components and Technology Conference (ECTC).
This study is conducted to develop advanced wafer thinning and handling system in 50μm thick TSV integration. Systematical investigation of the material compatibility between temporary bonding material and organic dielectric pairs is carried out in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6b0bc896be430e188a7b2eec7e34fbb
https://doi.org/10.1109/ectc.2011.5898767
https://doi.org/10.1109/ectc.2011.5898767