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pro vyhledávání: '"Kelvin Nelson"'
Autor:
Hao-Jan Chao, Venkat Ghanta, Kelvin Nelson, Shianling Wu, Jaga Shanmugavadivelu, Lizhen Yu, Jun Wu, Laung-Terng Wang, Jie Rao, Fe Zhuang, Jayanth Mekkoth
Publikováno v:
ISQED
This paper describes an application of a physical-design-friendly hierarchical logic built-in self-test (BIST) architecture and validation methodology on a networking system-on-chip (SOC) design. The design consists of two embedded cores, each contai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::acf1cfe8ad808d43560a7138c81bddc6
https://doi.org/10.1109/isqed.2012.6187466
https://doi.org/10.1109/isqed.2012.6187466
