Zobrazeno 1 - 10
of 25
pro vyhledávání: '"Kelvin Doong"'
Autor:
Andrzej J. Strojwas, Tomasz Brozek, Kelvin Doong, Indranil De, Xumin William Shen, Marcin Strojwas
Publikováno v:
2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM).
Autor:
Roberto Gonella, Tomasz Brozek, Meindert Lunenborg, J.-C. Giraudin, Christopher Hess, B. Martinet, Franck Arnaud, Laurent Garchery, Kelvin Doong, Christian Dutto
Publikováno v:
2019 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
FDSOI technology has been proposed as an alternative device scaling path which offers benefits of tunable, superior electrostatics transistor while maintaining simplicity of planar integration. New device type and integration elements brought up chal
Publikováno v:
MIXDES
Layout Design Rules have been scaled very aggressively to enable the 7nm technology node without EUV. As a result, achieving acceptable performance and yield in High Volume Manufacturing (HVM) has become an extremely challenging task. Systematic yiel
Publikováno v:
2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).
The observability of conventional electrical test site and imaging techniques needs to be extended and coupled with all of the actual product layout attributes in order to reflect the relevant yield detractors of the current technologies in productio
Publikováno v:
Journal of the Chinese Institute of Industrial Engineers. 27:281-293
Design for manufacturing is important in the deep-submicron regime. Increasing integrated circuit (IC) layout uniformity by adding non-functional metal lines in the empty area, so-called dummy feature filling, is an efficient and effective way to red
Autor:
L. J. Hung, Kelvin Doong, Sheng-Che Lin, T.J. Bordelon, Chien-Chih Liao, S.P.-S. Ho, Sunnys Hsieh, K.L. Young
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 21:169-179
This paper describes a common framework of test chip design for logic technology development and routine process monitoring, referred to as a field-configurable test structure array (FC-TSA), which can accommodate and test various types of test struc
Autor:
Philip Chia-Chi Lin, Kelvin Doong, K.L. Young, Sunnys Hsieh, Sheng-Che Lin, Chia-Chi Chu, Jurcy Cho-Hsi Huang, S.P.-S. Ho, Roger Wen-Lung Kang, Robin Chien-Jung Wang, L. J. Hung
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 17:123-141
This study aims to provide an integrated infrastructure for electrical-based dimensional process-window checking. The proposed infrastructure is comprised of design tools, testing programs, and analytical tools, providing an automatic and hierarchica
Autor:
Larg Weiland, Hans Eisenmann, Amit Joag, Kelvin Doong, Scott Lin, Sa Zhao, Balasubramania Murugan, Christopher Hess
Publikováno v:
2014 International Conference on Microelectronic Test Structures (ICMTS).
Due to recent changes in the manufacturing of FEOL (front end of line) layers it is increasingly difficult to provide rapid learning cycles required to drive yield improvement during new product introduction (NPI). The Direct Probe Characterization V
Autor:
Sunnys Hsieh, Che-Hsiung Hsu, Larg Weiland, Ding-Ming Kwai, Kelvin Doong, Jye-Yen Cheng, Christopher Hess, Binson Shen, Sheng-Che Lin
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 14:338-355
As technologies scale down, semiconductor manufacturing processes require more and more areas for test structures to ensure accurate yield estimation. This paper presents design guidelines for test structures with addressable failure sites to efficie
Publikováno v:
2009 IEEE International Conference on Microelectronic Test Structures.
To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process develo