Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Kehuey Wu"'
Publikováno v:
2020 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
Horizontally stacked Ge nanosheet GAA FETs are demonstrated, although Si, SiGe and GeSn stacked nanosheet FETs have been reported. The problem for formation of stacked pure-Ge nanostructures is that the Ge material is weaker than other IV group mater
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4c869c4ae6c2edbc4bd59c83aa78a2af
https://doi.org/10.1109/vlsi-tsa48913.2020.9203617
https://doi.org/10.1109/vlsi-tsa48913.2020.9203617
Publikováno v:
IEEE Electron Device Letters. 39:1133-1136
Horizontally stacked Ge-nanosheet gate-all-around FETs (GAAFETs) are demonstrated for the first time. The Ge/Si multilayers instead of the typically used Ge/SiGe ones were epitaxially grown as the starting material. To avoid island growth, the Ge/Si
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::08c0f21e638686ac1df4dd3503fc4ad1
https://doi.org/10.1109/led.2018.2850366
https://doi.org/10.1109/led.2018.2850366
Autor:
Wen-Kuan Yeh, An-Ni Dai, Wenqi Zhang, Po-Ying Chen, Yi-Lin Yang, Cheng-Li Lin, Tung-Huan Chou, Kwang-Jow Gan, Kehuey Wu, Chia-Hung Shih
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 16:610-616
In this paper, the impact of width quantization on device characteristic and stressing induced device degradation for high-k/metal tri-gate n/p-type FinFET was investigated well including electrical characteristic clarification and simulation. Carrie
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2570dda354397d8032b752ac8d81a786
https://doi.org/10.1109/tdmr.2016.2612703
https://doi.org/10.1109/tdmr.2016.2612703
Autor:
Guang-Li Luo, Bo-Yuan Chen, Kehuey Wu, Chien-Chung Hsu, Chun-Lin Chu, Shih-Hong Chen, Wen-Fa Wu, Kun-Lin Lin, Wen-Kuan Yeh
Publikováno v:
2019 Silicon Nanoelectronics Workshop (SNW).
Horizontally five stacked pure-Ge nanosheets (NSs) GAA FETs are demonstrated. In this device process, we intentionally grow large mismatch Ge/Si multilayers rather than Ge/GeSi multilayers as the starting material, because the large difference of mat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::30230a6ef25d7cbcfb4b5c0e8a570abd
https://doi.org/10.23919/snw.2019.8782970
https://doi.org/10.23919/snw.2019.8782970
Publikováno v:
IEEE Transactions on Nanotechnology. 14:330-337
In this study, we investigate the impact of junction doping distribution (LDD/halo) on variations and asymmetry of device characteristics for fully depleted silicon on insulator (FDSOI) with ultrathin buried oxide layer nMOSFET. The device performanc
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c3f0b54313563025f9f024305de1c9a
https://doi.org/10.1109/tnano.2015.2394247
https://doi.org/10.1109/tnano.2015.2394247
Publikováno v:
2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
Detailed comparisons of FinFETs with triangular and rectangular fins were performed using numerical simulations. Although, with the same leakage current (Ioff), the on current (Idsat) of the triangular fin is less than that of the rectangular one, th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::685aeac4041d9b3f07e25796a0e7e7b1
https://doi.org/10.1109/sispad.2013.6650595
https://doi.org/10.1109/sispad.2013.6650595
Autor:
Ren-Jei Chung, Chenming Hu, Fu-Ju Hou, Po-Jung Sung, Kehuey Wu, Fu-Liang Yang, Chia-Wei Ho, Yao-Jen Lee, Chao-An Jong, Bing-Mau Chen, Ying-Hao Su, Wen-Fa Wu, Mei-Yi Lee
Publikováno v:
2011 International Electron Devices Meeting.
Very high 6.5 aspect ratio, 30nm diameter contacts are filled with a novel bottom-up Ag electroplating technology for the first time. The technology utilizes two distinct advantages of Ag over Cu: (1) Ag has the lower metal resistivity, and (2) Ag ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31f308fb98a26ed5eb2a1fc5f00518c9
https://doi.org/10.1109/iedm.2011.6131509
https://doi.org/10.1109/iedm.2011.6131509
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
We have demonstrated successfully the integration scheme of metallized source/drain extension (M-SDE) with state-of-the-art strained-Si technique. Drain currents of N-FET (Lgate = 40 nm) and P-FET (Lgate = 35 nm) with M-SDE can achieve 1620 muA/mum a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b305deb2e4d327ed5ffeca74c5c20aee
https://doi.org/10.1109/vlsit.2007.4339750
https://doi.org/10.1109/vlsit.2007.4339750
Publikováno v:
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
A simple yet effective approach for the extraction of source/drain (S/D) series resistance RSD using mechanical four-point bending is presented. This new approach can be used to extract the RSD of each device disregarding its channel length. Accordin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0b0d5846cada2646bf1727359471ebdc
https://doi.org/10.1109/vtsa.2007.378920
https://doi.org/10.1109/vtsa.2007.378920
Publikováno v:
2007 International Symposium on VLSI Technology, Systems & Applications (VLSI-TSA); 2007, p1-2, 2p