Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Keerthikumara Devarajegowda"'
Autor:
Endri Kaja, Nicolas Gerlin, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
Publikováno v:
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c382d6e0172ca2a6e4d901908beb964e
https://doi.org/10.1109/dft56152.2022.9962369
https://doi.org/10.1109/dft56152.2022.9962369
Autor:
Nicolas Gerlin, Endri Kaja, Monideep Bora, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Wolfgang Ecker
Publikováno v:
2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48733ea8be627e2e098a4d1f58355de4
https://doi.org/10.1109/vlsi-soc54400.2022.9939622
https://doi.org/10.1109/vlsi-soc54400.2022.9939622
Autor:
Edoardo Mosca, Elena Zennaro, Wolfgang Ecker, Lorenzo Servadei, Michael Werner, Keerthikumara Devarajegowda, Robert Wille
Publikováno v:
IEEE Transactions on Computers. 69:856-867
Hardware/software co-designs are usually defined at high levels of abstractions at the beginning of the design process in order to provide a variety of options on how to realize a system. This allows for design exploration which relies on knowing the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a48d2ecd1a1bb731ccb3e8b5c9b14c88
https://doi.org/10.1109/tc.2020.2968888
https://doi.org/10.1109/tc.2020.2968888
Publikováno v:
DAC
The scalable and extendable RISC-V ISA introduced a new level of flexibility in designing highly customizable processors. This flexibility in processor designs adds to the complexity of already complex functional verification process. Although formal
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b69d6531383d8d458bd9fafa25146268
https://doi.org/10.1109/dac18074.2021.9586264
https://doi.org/10.1109/dac18074.2021.9586264
Autor:
Zhao Han, Wolfgang Ecker, Sebastian Prebeck, Daniela Sanchez Lopera, Keerthikumara Devarajegowda, Bowen Li, Gabriel Rutsch, Deyan Wang
Publikováno v:
VLSI-SoC
Despite the high configurability of IPs and hardware generators, code modifications are still required to introduce aspect-oriented instrumentation to satisfy emerging design requirements such as on-chip debug and functional safety. These code modifi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1e9eadb8a9b2042cc75b1c79c30e09be
https://doi.org/10.1109/vlsi-soc53125.2021.9606984
https://doi.org/10.1109/vlsi-soc53125.2021.9606984
Autor:
Endri Kaja, Wolfgang Ecker, Keerthikumara Devarajegowda, Zhao Han, Heimo Hartlieb, Varsha Bhupal Bavache
Publikováno v:
2020 17th Biennial Baltic Electronics Conference (BEC).
Fault tolerance enables the system to avoid threats (fail-safe) or continue with its safe operational functionality even in the presence of random faults. This ability comes at the cost of additional development efforts and the silicon overhead requi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::038b32f3b4e5488d40ad137bcc95ca72
https://doi.org/10.1109/bec49624.2020.9276994
https://doi.org/10.1109/bec49624.2020.9276994
Autor:
Robert Wille, Keerthikumara Devarajegowda, Edoardo Mosca, Michael Werner, Lorenzo Servadei, Wolfgang Ecker
Publikováno v:
ACM Great Lakes Symposium on VLSI
The complexity of today's System on Chips (SoCs) forces designers to use higher levels of abstractions. Here, early design decisions are conducted on abstract models while different configurations describe how to actually realize the desired SoC. Sin
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::712fabbe0a2d6d16ab57aaabcdc8cbc8
https://doi.org/10.1145/3386263.3406950
https://doi.org/10.1145/3386263.3406950
Autor:
Wolfgang Ecker, Clark Barrett, Mohammad Rahmani Fadiheh, Eshan Singh, Keerthikumara Devarajegowda, Dominik Stoffel, Wolfgang Kunz, Subhasish Mitra
Publikováno v:
DATE
The required manual effort and verification expertise are among the main hurdles for adopting formal verification in processor design flows. Developing a set of properties that fully covers all instruction behaviors is a laborious and challenging tas
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47d6dd35ab58242c4774fc91b2e35849
https://doi.org/10.23919/date48585.2020.9116515
https://doi.org/10.23919/date48585.2020.9116515
Publikováno v:
NORCAS
Design productivity remains a big problem in current embedded system development. Domain-Specific Languages (DSLs) are a promising measure to accelerate the development cycle. However, the inconsistent syntax in various DSLs, during system developmen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c8b8eca2258c14e9fbb2055a9ae8dc91
https://doi.org/10.1109/norchip.2019.8906949
https://doi.org/10.1109/norchip.2019.8906949
Publikováno v:
DSD
This paper presents a practical methodology for applying formal verification on industrial designs. The methodology is developed considering the quality, efficiency and productivity required in an industrial verification setup. The flow proposes a sy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5832937e0b15a5ec1d10eacdfa4ad90e
https://doi.org/10.1109/dsd.2019.00094
https://doi.org/10.1109/dsd.2019.00094