Zobrazeno 1 - 1
of 1
pro vyhledávání: '"Kee-Bum Shin"'
Publikováno v:
2013 International SoC Design Conference (ISOCC).
A full-speed USB 2.0 device PHY IP chip is implemented in FPGA by using a Verilog synthesis. It works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX. The TX and RX circuits include a NRZI encoder/decode
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3add0b9af68cc27f93b274c9b2f3dc95
https://doi.org/10.1109/isocc.2013.6863961
https://doi.org/10.1109/isocc.2013.6863961
