Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Kee Hian Tan"'
Autor:
Mayank Raj, Chuan Xie, Ade Bekele, Adam Chou, Wenfeng Zhang, Ying Cao, Jae Wook Kim, Nakul Narang, Hongyuan Zhao, Yipeng Wang, Kee Hian Tan, Winson Lin, Jay Im, David Mahashin, Santiago Asuncion, Parag Upadhyaya, Yohan Frans
Publikováno v:
2023 IEEE International Solid- State Circuits Conference (ISSCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c99fe5715e242bd0f315516540e7e48c
https://doi.org/10.1109/isscc42615.2023.10067617
https://doi.org/10.1109/isscc42615.2023.10067617
Autor:
Jae Wook Kim, Chuen-huei Adam Chou, Kee Hian Tan, Kun-Yung Ken Chang, Adebabay M. Bekele, Yohan Frans, H. Ahn, Ilias Chlis, Yipeng Wang, Arianne Roldan, David Mahashin, H.-W. Hung, Stanley Chen, Lei Zhou, Declan Carey, Hongtao Zhang, Ronan Casey, Jay Im, Ying Cao, Winson Lin, Kevin Zheng
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:7-18
A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d4a37bd68a77c15acd26014ce64d6ef
https://doi.org/10.1109/jssc.2020.3024261
https://doi.org/10.1109/jssc.2020.3024261
Autor:
Yipeng Wang, Junho Cho, Eugene Ho, Ma Shaojun, Asma Laraba, Yohan Frans, Daniel Wu, Kee Hian Tan, Wenfeng Zhang, Chi Fung Poon, Ying Cao, Parag Upadhyaya, Winson Lin
Publikováno v:
VLSI Circuits
This paper describes the design of a 1.24pJ/b 112Gb/s PAM4 transceiver testchip in 7nm FinFET for in-package die-to-die communication. The receiver supports 0-1.2V input common mode and utilizes a single-stage active inductor-based CMOS CTLE with 12
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::37a5c9766c179cc02c04d20328c043d6
https://doi.org/10.23919/vlsicircuits52068.2021.9492467
https://doi.org/10.23919/vlsicircuits52068.2021.9492467
Autor:
Nakul Narang, Siok Wei Lim, Bruce Xu, Kee Hian Tan, Toan Pham, Wenfeng Zhang, Junho Cho, Geoff Zhang, Chi Fung Poon, Hongtao Zhang, Parag Upadhyaya, Winson Lin, Jin Namkoong, Yohan Frans, Ken Chang, Arianne Roldan
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:18-28
The design of a dual-mode, 19–58-Gb/s four-level pulse-amplitude modulation (PAM-4) and 9.5–29-Gb/s nonreturn to zero (NRZ), transceiver in 16-nm FinFET is presented. The fully adaptive receiver consists of a multi-stage continuous time linear eq
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b6899a9c54618499489997b2dbff50c2
https://doi.org/10.1109/jssc.2018.2875091
https://doi.org/10.1109/jssc.2018.2875091
Autor:
Yohan Frans, Hongtao Zhang, David Mahashin, Winson Lin, Yipeng Wang, Jay Im, Stanley Chen, Ken Chang, Adam Chou, Kevin Zheng, Hao-Wei Hung, Arianne Roldan, Ying Cao, Lei Zhou, Declan Carey, Ilias Chlis, Hong Ahn, Jae Wook Kim, Kee Hian Tan, Ronan Casey, Ade Bekele
Publikováno v:
ISSCC
Interest in 112Gb/s wireline transceivers targeting data center and communication applications has rapidly increased. PAM-4 signaling remains the dominant choice of modulation scheme due to its superior spectral efficiency [1-2]. This paper reports a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e96a0bf1319d2d9472a50d749861e697
https://doi.org/10.1109/isscc19947.2020.9063081
https://doi.org/10.1109/isscc19947.2020.9063081
Autor:
Bruce Xu, Ronan Casey, Haibing Zhao, Mayank Raj, James Hudner, Ken Chang, Kee Hian Tan, Hongtao Zhang, Ted Lee, Neto Pedro W, Winson Lin, Declan Carey, Nakul Narang, Marc Erett, Ping-Chuan Chiang, Hongyuan Zhao, Arianne Roldan, Kevin Geary, Yohan Frans
Publikováno v:
CICC
A multi-lane short-reach wireline transceiver is implemented in 16nm FinFET. Taking advantage of a low-loss channel with minimum reflections, 56Gbps NRZ differential signaling is employed, using only a continuous time linear equalizer (CTLE) in the r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1f27cc4cf8da535bc6cd86c032ef257
https://doi.org/10.1109/cicc.2019.8780221
https://doi.org/10.1109/cicc.2019.8780221
Autor:
Sai Lalith Chaitanya Ambatipudi, Ken Chang, Arianne Roldan, Hongyuan Zhao, Haibing Zhao, Yipeng Wang, Parag Upadhyaya, Yohan Frans, Kee Hian Tan, Nakul Narang, Ping-Chuan Chiang, Siok Wei Lim, Declan Carey
Publikováno v:
VLSI Circuits
This work reports a 112-Gb/s low power voltage-mode transmitter (TX) with four-tap feed forward equalization (FFE), designed and fabricated in 16nm FinFET technology. The design includes a hybrid impedance controller with dual regulator architecture
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::26f92266d8994fe72d8c4ff5a890b617
https://doi.org/10.1109/vlsic.2018.8502273
https://doi.org/10.1109/vlsic.2018.8502273
Autor:
David Mahashin, Tim Cronin, Adebabay M. Bekele, Stanley Chen, Hongyuan Zhao, Ian Zhuang, Parag Upadhyaya, Adam Chou, Winson Lin, Kee Hian Tan, Dave Freitas, Lei Zhou, Kok Lim Chan, Yohan Frans, Jay Im, Ken Chang, Didem Turker
Publikováno v:
VLSI Circuits
A 28Gb/s NRZ wireline transceiver is implemented in 7nm FinFET. A transformer-based LC-PLL sends a single-phase differential clock to the voltage-mode transmitter and the receiver. Local multi-phase clocks are generated in each TX/RX lane to support
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a606e18857359c188a9c7a651cf4104b
https://doi.org/10.1109/vlsic.2018.8502275
https://doi.org/10.1109/vlsic.2018.8502275
Autor:
Scott McLeod, Arianne Roldan, Marc Erett, Ronan Casey, Mayank Raj, Ken Chang, Haibing Zhao, Yohan Frans, Kevin Geary, James Hudner, Declan Carey, Neto Pedro W, Hongyuan Zhao, Kee Hian Tan, Hongtao Zhang, Ping-Chuan Chiang
Publikováno v:
ISSCC
The industry has recently proposed standards for synchronous high-speed interfaces targeting chip-to-chip communication across a very short PCB trace [1]. Figure 16.7.1 shows an example of such an interface. Eight 56Gb/s NRZ lanes provide a total of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0adf0202e9d94cb839f9354519e08491
https://doi.org/10.1109/isscc.2018.8310290
https://doi.org/10.1109/isscc.2018.8310290
Autor:
Nakul Narang, Kee Hian Tan, Geoff Zhang, Siok Wei Lim, Chi Fung Poon, Toan Pham, Yohan Frans, Junho Cho, Jin Namkoong, Bruce Xu, Arianne Roldan, Ken Chang, Wenfeng Zhang, Hongtao Zhang, Winson Lin, Parag Upadhyaya
Publikováno v:
ISSCC
Trends in IoT and cloud computing continue to accelerate bandwidth demand, requiring technology innovation to cover 50G, 100G and 400G ports without significant increase in cost or power per bit. In order to mitigate the cost of infrastructure upgrad
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22360100003030795120f09ae8fbde77
https://doi.org/10.1109/isscc.2018.8310207
https://doi.org/10.1109/isscc.2018.8310207