Zobrazeno 1 - 10
of 60
pro vyhledávání: '"Ke-Wei Su"'
Autor:
J. Cai, B. Pulicherla, C. L. Chen, Subhadeep Mukhopadhyay, K. F. Yu, J. F. Wang, H. L. Chiang, W. S. Khwa, W. K. Lee, H.-S. P. Wong, Ke-Wei Su, T. C. Chen, Tahui Wang, P. J. Liao, Carlos H. Diaz
Publikováno v:
2020 IEEE Symposium on VLSI Technology.
We present advanced FinFET characterization and circuit analysis at reduced temperatures down to 77 K. Steepened subthreshold slope enables threshold voltage $(V_{\mathrm{TH}})$ and supply voltage $(V_{\mathrm{DD}})$ scaling for $\sim 0.27\times$ pow
Autor:
Clement Huang, Li Chung Hsu, Julian Chen, Kasa Huang, Jim Liang, Cheng Hsiao, Chung-Kai Lin, Ke-Wei Su, Wai-Kit Lee, Min-Chie Jeng
Publikováno v:
2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
In this paper we not only discuss how to implement the recovery effect with TMI but also give various examples to show that without considering the recovery effect, the design margin of a system can be either under- or over-estimated. To validate our
Autor:
Ke-Ying Su, Te-Yu Liu, Chung-Kai Lin, King-Ho Tam, Min-Chie Jeng, Cheng Tai-Yu, Kevin Chen, Cheng Hsiao, Jun-Fu Huang, Ke-Wei Su, Kuo-Pei Lu, Joshua Sun, Chun Cheng, Katherine Chiang
Publikováno v:
2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
A comprehensive variation model is critical to achieve both competitive design and manufacturing yield in advanced technologies. Conventionally, as long as FEOL (front end of line) statistical model is appropriate, BEOL (back end of line) variations
Publikováno v:
Japanese Journal of Applied Physics. 46:1870-1873
This paper presents an inversion capacitance–voltage (C–V) reconstruction method for long-channel metal oxide semiconductor field effect transistors (MOSFETs) using the BSIM4/SPICE and the intrinsic input resistance (Rii) model. The concept of Ri
Autor:
Sheng-Jier Yang, Ming-Jer Chen, Chih-Chiang Wang, Yi-Ming Sheu, Ke-Wei Su, S. Tian, Sally Liu
Publikováno v:
IEEE Transactions on Electron Devices. 53:2792-2798
The well-edge proximity effect caused by ion scattering during implantation in highly scaled CMOS technology is explored from a physics and process perspective. Technology computer-aided design (TCAD) simulations together with silicon wafer experimen
Publikováno v:
IEEE Transactions on Electron Devices. 53:2559-2563
This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation res
Publikováno v:
IEEE Transactions on Electron Devices. 53:2179-2186
In advanced CMOS technologies, transistor characteristics depend not only on the layout of the device itself but also on the layout of the adjacent structures. For the compact model to accurately predict circuit behavior, it needs information about t
Publikováno v:
IEEE Transactions on Electron Devices. 53:1373-1378
This paper reports the gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO/sub 2/ high-k gate dielectric considering vertical and fringing displacement effects. Based on the
Autor:
Ke-Wei Su, Kasa Huang, Juan-Yi Chen, Min-Chie Jeng, Wai-Kit Lee, Cheng Hsiao, Chung-Kai Lin, Jim Liang
Publikováno v:
2014 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).
In this paper, we discuss how to implement the self heating and aging models with TMI. Various examples about self heating and aging simulations with TMI methodology are shown in this paper. Without trading-off the accuracy, the one with proposed TMI
Publikováno v:
CICC
Using simulation to assess the impacts of various reliability mechanisms to circuit performance has become prevail for advanced technologies due to smaller headroom (=Vdd-Vth) and less design margins. This paper reviews existing circuit aging simulat