Zobrazeno 1 - 10
of 67
pro vyhledávání: '"Kazuyasu Fujishima"'
Autor:
Hideyuki Noda, Katsumi Dosaka, Tsutomu Yoshihara, Kazuyasu Fujishima, Kazunari Inoue, Kenji Anami, Tetsushi Koide, Hans Jurgen Mattausch, Kazutami Arimoto
Publikováno v:
IEICE Transactions on Electronics. :622-629
This paper describes a dynamic TCAM architecture with planar complementary capacitors, transparently scheduled refresh (TSR), autonomous power management (APM) and address-input-free writing scheme. The complementary cell structure of the planar dyna
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::187d985fcc7ee9b9cbd6213475faaf38
https://doi.org/10.1093/ietele/e88-c.4.622
https://doi.org/10.1093/ietele/e88-c.4.622
Autor:
Kazutami Arimoto, Hideyuki Ozaki, T. Yoshihara, S. Maeda, T. Yamauchi, F. Morisita, Kazuyasu Fujishima
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1169-1178
This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b46ebdd598048f6451e892360c1f3797
https://doi.org/10.1109/4.859506
https://doi.org/10.1109/4.859506
Autor:
Shigeki Tomishima, Mikio Asakura, Tsukasa Ooishi, Kazuyasu Fujishima, Kazutami Arimoto, Hideto Hidaka
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:432-440
Proposes an advanced DRAM array driving technique which can achieve low-voltage operation, a well-synchronized sensing and equalizing method. This method sets the DRAM array free from the body effect, achieves a small influence of the short channel e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d520699e2b4d87979e9a160674fa21ed
https://doi.org/10.1109/4.280692
https://doi.org/10.1109/4.280692
Autor:
Katsuhiro Suma, Y. Yamaguchi, Kazutami Arimoto, Yasuo Inoue, Kazuyasu Fujishima, Toshiyuki Oashi, Hideto Hidaka, Tadashi Nishimura, M. Hirose, Takahiro Tsuruda, T. Yoshihara, Takahisa Eimori, F. Morishita, T. Iwamatsu
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:1323-1329
For future ULSI DRAMs beyond the 256 Mb generation, several circuit techniques and memory cell structures have been proposed to meet the requirement of high performance at low voltage. These solutions frequently involve complicated processing steps a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::386229824c8df08778f1aa542d4e2108
https://doi.org/10.1109/4.328631
https://doi.org/10.1109/4.328631
Autor:
Kazuyasu Fujishima, Hideto Hidaka, Katsuhiro Suma, Masanori Hayashikoshi, Masaki Tsukude, Yasuhiro Konishi, Kazutami Arimoto
Publikováno v:
IEEE Design & Test of Computers. 10:6-12
Two testing techniques for ultra-large-scale integrated (ULSI) memories containing on-chip voltage downconverters (VDCs) are described. The first in an on-chip VDC tuning technique that adjusts internal V/sub CC/ to compensate for the monitored chara
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ce65be9d8f1059cf60bef8dcaf24ab8c
https://doi.org/10.1109/54.211523
https://doi.org/10.1109/54.211523
Autor:
Mikio Asakura, Masanori Hayashikoshi, Kazuyasu Fujishima, K. Tanaka, Kazutami Arimoto, Masaki Tsukude, Hideto Hidaka, Katsuhiro Suma, Y. Ohno, Tsukasa Oishi, Yasuhiro Konishi, Kazutoshi Hirayama, W. Wakamiya, Shinji Kawai
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1020-1027
A high-speed 16-Mb DRAM with high reliability is reported. A multidivided column address decoding scheme and a fully embedded sense-amplifier driving scheme were used to meet the requirements for high speed. A low-power hybrid internal power supply v
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::66dd4ab632ac586cd993579a743d131e
https://doi.org/10.1109/4.142597
https://doi.org/10.1109/4.142597
Cell-plate line connecting complementary bit-line (C/sup 3/) architecture for battery-operated DRAMs
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:597-602
In low-voltage operating DRAMs, one of the most serious problems is how to maintain sufficient charge stored in the memory cell, which is concerned with the operating margin and soft error immunity. An array architecture called the cell-plate line co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::648ca273a42e6d268246583062538fb1
https://doi.org/10.1109/4.126549
https://doi.org/10.1109/4.126549
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:610-617
A high-density dual-port DRAM architecture is proposed. It realizes a two-transistor/one-capacitor (2Tr-1C) dual-port memory cell array with immunity against the array noise caused by the dual-port operation. This architecture, called a truly dual-po
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::50926cca274a479419df2d1dcd8cdae4
https://doi.org/10.1109/4.126551
https://doi.org/10.1109/4.126551
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:569-573
A dual-mode sensing (DMS) scheme for a capacitor-coupled EEPROM cell is described. A memory cell structure and a sensing scheme are proposed and estimated. The memory cell combines an EEPROM cell with a DRAM cell. The DMS scheme utilizes the charge-m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::47fc19b9a1a59bc980e6afe07dd32810
https://doi.org/10.1109/4.126545
https://doi.org/10.1109/4.126545
Publikováno v:
IEEE Micro. 10:14-25
A DRAM (dynamic RAM) with an on-chip cache, called the cache DRAM, has been proposed and fabricated. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technolo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6e451d54a7e0ac45ec346ee867e82594
https://doi.org/10.1109/40.52944
https://doi.org/10.1109/40.52944