Zobrazeno 1 - 10
of 21
pro vyhledávání: '"Kazuya Uejima"'
Autor:
Takashi Hase, Hiroshi Sunamura, Koji Masuzaki, Koichi Takeda, Akira Tanabe, Akira Mitsuiki, Kazuya Uejima, M. Narihiro, N. Furutake, Yoshihiro Hayashi, Makoto Ueki
Publikováno v:
IEEE Transactions on Electron Devices. 64:419-426
A low-power 2-Mb Resistance random access memory (ReRAM) macro is developed in a 90-nm CMOS platform with a 3-nm-thick TaO x /Ta2O5 switching layer of the active area of $0.01~\mu \text{m}^{2}$ . Instability of the ON-state minority bits degrades the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::539592b8fcea8a9c3d972b2059947623
https://doi.org/10.1109/ted.2016.2639283
https://doi.org/10.1109/ted.2016.2639283
Publikováno v:
Microelectronic Engineering. 35:245-248
Two dimensional arrays of Ga droplets on the CaF 2 film were fabricated by the site control technique using electron beam surface modification. Spacing of each droplet can be close to each other to the effective beam spot size at the As CaF 2 interfa
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c70285bdd8bf573ef1fbca29b67248e2
https://doi.org/10.1016/s0167-9317(96)00104-9
https://doi.org/10.1016/s0167-9317(96)00104-9
Publikováno v:
Physica B: Condensed Matter. 227:303-306
Site-controlled Ga droplet formation using modification of fluoride surface by electron beam exposure was investigated as a new nanofabrication technique. A single linear array of Ga droplets of approximately 10 nm in diameter on CaF2 film was obtain
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1450382d7b389a180eef4d367e8ac62f
https://doi.org/10.1016/0921-4526(96)00426-7
https://doi.org/10.1016/0921-4526(96)00426-7
Autor:
Takashi Hase, Toshiharu Nagumo, K. Yako, Akira Mineji, T. Ikezawa, Masami Hane, Seiichi Shishiguchi, Kazuya Uejima, Toyoji Yamamoto, N. Matsuzaka
Publikováno v:
2008 IEEE International Electron Devices Meeting.
An aggressive junction design concept is proposed for further scaling of bulk CMOS featuring selective epi-growth raised source/drain extentions (RSDext) in conjunction with high temperature millisecond annealing (MSA) process. The junction design wi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::84417b58809aadcfd2c5e3455927f56d
https://doi.org/10.1109/iedm.2008.4796848
https://doi.org/10.1109/iedm.2008.4796848
Publikováno v:
2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors.
We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B 18 H 22 ) implantation and high-temperature millisecond annealing processes and a f
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45d5a05c738fee71eb186968e9e0af79
https://doi.org/10.1109/rtp.2008.4690561
https://doi.org/10.1109/rtp.2008.4690561
Autor:
M. Narihiro, Akira Mineji, Seiichi Shishiguchi, T. Nagumo, Masami Hane, M. Tanaka, Nobuyuki Ikarashi, Kazuya Uejima, K. Yako
Publikováno v:
Extended Abstracts - 2008 8th International Workshop on Junction Technology (IWJT '08).
The formation of ultra-shallow junction (USJ) less than 10 nm by using diffusion-less high-activation millisecond annealing technique has been investigated for deeply scaled planar bulk CMOS. This achievement relies on cross-sectional visualization o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eee367351f71ca2f7ffe4d3aa9be2198
https://doi.org/10.1109/iwjt.2008.4540019
https://doi.org/10.1109/iwjt.2008.4540019
Autor:
Nobuyuki Ikarashi, Kazuya Uejima, Takeo Ikezawa, Toshinori Fukai, Akio Toda, Masami Hane, Edmund G. Seebauer, Susan B. Felch, Amitabh Jain, Yevgeniy V. Kondratenko
Publikováno v:
AIP Conference Proceedings.
Cross‐sectional electron holography was used for two‐dimensional potential mapping of source/drain extensions (SDEs) in scaled MOSFETs fabricated using state‐of‐the‐art junction formation technology. First, we show that specimen‐preparati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c4ff3131e873ae578d7c45927ec056e5
https://doi.org/10.1063/1.3033686
https://doi.org/10.1063/1.3033686
Publikováno v:
2007 IEEE Symposium on VLSI Technology.
Double disposable sidewall spacers (DDSW) process and adhesion reinforcement technique (ART) are proposed, for the first time, demonstrating efficient stress-transfer from the dual stress liner (DSL) to the FET channel region. A thin L-shape sidewall
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cf57654169b14150b89c66e959b1fd38
https://doi.org/10.1109/vlsit.2007.4339700
https://doi.org/10.1109/vlsit.2007.4339700
Autor:
Masami Hane, T. Nagumo, K. Yako, M. Narihiro, Kazuya Uejima, Seiichi Shishiguchi, Akira Mineji, M. Tanaka, Nobuyuki Ikarashi
Publikováno v:
2007 IEEE International Electron Devices Meeting.
The scaling limit of planar bulk MOSFETs with ultra-shallow junction (USJ) by using diffusion-less high-activation annealing technique has been investigated. Incorporation of cluster-ion (B18H22) implantation for PFETs and high-temperature msec-annea
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f085c1a70cb0023fbae54948f4ddbcc8
https://doi.org/10.1109/iedm.2007.4418887
https://doi.org/10.1109/iedm.2007.4418887
Autor:
T. Fukase, H. Nakamura, I. Yamamoto, Kazuya Uejima, N. Kimizuka, Toru Tatsumi, Toshiyuki Iwamoto, T. Nakayama, Kiyotaka Imai, Y. Nakahara, K. Taniguchi, T. Abe, K. Masuzaki
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
A 55nm node low standby power/generic CMOS technology is demonstrated. The transistor deploys the combination of high-k gate dielectric film and process-induced stress technologies. It features high drive currents with low leakage, wide coverage of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d60a5199c7c77cdf7b7905d31f25dfeb
https://doi.org/10.1109/vlsit.2006.1705265
https://doi.org/10.1109/vlsit.2006.1705265