Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Kazuo Sukegawa"'
Autor:
Ikuhiro Yamamura, Satoshi Yamaguchi, Yoshihiro Takao, Hiroshi Kudo, Naoki Nagashima, Michiari Kawano, Yoshiyuki Kotani, Satoru Asai, Nobuhisa Naori, Keizaburo Yoshie, Takashi Nagano, Masaya Uematsu, Kazuo Sukegawa, Shingo Kadomura, Junichi Mitani
Publikováno v:
Microelectronics Reliability. 42:15-25
This paper describes a 0.11 μm CMOS technology with high-reliable copper (Cu) and very low k (VLK) (k
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9a581a0e42dbd8d548babb7f774476ce
https://doi.org/10.1016/s0026-2714(01)00233-5
https://doi.org/10.1016/s0026-2714(01)00233-5
Autor:
Toshihiko Mori, R. Sasagawa, Shoichiro Kawashima, Kazuo Sukegawa, I. Fukushi, Shigetoshi Wakayama, M. Hamaminato
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:793-799
This paper proposes and reports a low-power SRAM using a charge-transfer (CT) pre-sense amplifier and a bus signal encoding scheme. The CT amplifier overcomes the V/sub th/ relative difference between the pair MOS transistors, and thus reduces the in
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c7418b6f4b30f59d42795a0064787590
https://doi.org/10.1109/4.668995
https://doi.org/10.1109/4.668995
Autor:
M. Nishikawa, Kazuo Sukegawa, T. Miyashita, Takae Sukegawa, H. Kurata, T. Yamamoto, K. Hashimoto, Keiji Ikeda, Naoyoshi Tamura, Masataka Kase, Y. Shimamune, A. Hatada, Y. S. Kim, Tomohiro Kubo, M. Fukuda
Publikováno v:
Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b207399f8b2026dd42f89b4bae9ff5ce
https://doi.org/10.7567/ssdm.2008.b-3-5l
https://doi.org/10.7567/ssdm.2008.b-3-5l
Autor:
M. Nishikawa, H. Nagai, Y. S. Kim, Hiroyuki Ohta, Kenichi Okabe, K. Ohkoshi, Keiji Ikeda, Takae Sukegawa, Masataka Kase, S. Satoh, Tomohiro Kubo, Akiyoshi Hatada, H. Kurata, Y. Hayami, Kazuo Sukegawa, Naoyoshi Tamura, Toshihiro Sugii, T. Miyashita, Y. Shimamune, T. Yamamoto
Publikováno v:
2008 Symposium on VLSI Technology.
We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::22438818682cf356ce5ceec3ed08cada
https://doi.org/10.1109/vlsit.2008.4588613
https://doi.org/10.1109/vlsit.2008.4588613
Autor:
Kenichi Okabe, Keiji Ikeda, Masataka Kase, Akiyoshi Hatada, Kazuo Sukegawa, Toshihiro Sugii, S. Satoh, Y. Shimamune, Y. S. Kim, T. Miyashita, H. Kurata, Hiroyuki Ohta, H. Fukutome, Hiroshi Morioka, M. Fukuda, Y. Hayami, Naoyoshi Tamura, Kazuo Kawamura, M. Tajima, J. Ogura
Publikováno v:
2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
Direct comparison between competitive process flows showed that the eSiGe-S/D-last flow is the most promising CMOS integration process for manufacturing 45-nm technology node and beyond because it has good extensibility with various performance boost
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::badcfb034fb8dd173794ef4d8439f12c
https://doi.org/10.1109/vtsa.2008.4530828
https://doi.org/10.1109/vtsa.2008.4530828
Autor:
Toshihiro Sugii, Akiyoshi Hatada, Kazuo Sukegawa, K. Ohkoshi, Keiji Ikeda, Toshihiko Mori, M. Tajima, H. Fukutome, S. Satoh, Kenichi Okabe, Naoyoshi Tamura, Hiroyuki Ohta
Publikováno v:
2007 IEEE International Electron Devices Meeting.
A new powerful strain booster named as dopant confinement layer (DCL) technique is proposed for the first time. DCL technique is a novel stress memorization technique (SMT). Our proposed method doesn't require any additional capping layers used in SM
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d54265938a4f5e6b2d7251fbdeaa9558
https://doi.org/10.1109/iedm.2007.4418925
https://doi.org/10.1109/iedm.2007.4418925
Autor:
Toshiro Futatsugi, Hiroki Futatsuya, Keiji Ikeda, M. Terahara, Atsuhiro Tsukune, Toshihiro Sugii, T. Arita, E. Yoshida, M. Osawa, Masataka Kase, Y. Shimoda, M. Kojima, M. Okuno, T. Watanabe, T. Shirasu, Ken Sugimoto, Michie Sunayama, M. Tajima, Y. Sanbonsugi, H. Ochimizu, S. Satoh, M. Fukuda, Teruyoshi Yao, H. Kurata, J. Ogura, Hisaya Sakai, M. Oryoji, M. Yamaji, Hiroshi Kudo, Y. Mizushima, Kazuo Sukegawa, T. Yamamoto
Publikováno v:
2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
A 45 nm low-cost LSTP CMOS technology is presented. This technology features advanced ArF lithography using SRAF, low-leak transistors fabricated by optimized SiON and S/D junction design, CoSi2, SRAM cell with acceptable operational margin, and full
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c39111776afecd90f51388069bdc3a7
https://doi.org/10.1109/vtsa.2007.378960
https://doi.org/10.1109/vtsa.2007.378960
Autor:
Y. Hayami, Kazuo Kawamura, T. Sakuma, Kazuo Sukegawa, Masashi Shima, Shintaro Sato, Tamotsu Owada, K. Okoshi, Shunichi Fukuyama, Ken Sugimoto, K. Hosaka, Hiroshi Minakata, H. Kokura, K. Hashimoto, H. Ota, Tsunehisa Sakoda, Takayuki Aoyama, Naoyoshi Tamura, Motoshu Miyajima, Toshihiko Mori, Satoshi Nakai, J. Ogura, Akira Katakami, Akiyoshi Hatada, Kenichi Okabe, T. Miyashita, Y. Shimamune, Akio Yamaguchi, Hiroshi Morioka, Sergey Pidin, M. Kojima, T. Watanabe, Toshihiro Sugii, H. Fukutome, M. Okuno, Masafumi Nakaishi, T. Isome
Publikováno v:
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
High-performance low operation power (LOP) transistors were developed for 45nm node universal applications. A high uniaxial strain and low resistance NiSi technique, enhanced by a slit under the slim and high Young's modulus (YM) offset spacer covere
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ec7c0fb344f80cd899d787b5e9b80f47
https://doi.org/10.1109/vlsit.2006.1705264
https://doi.org/10.1109/vlsit.2006.1705264
Autor:
Takayoshi Minami, Toshihiro Sugii, K. Hashimoto, Akira Katakami, Y. Shimamune, S. Satoh, Toshihiko Mori, Y. Hayami, Motoshu Miyajima, Akiyoshi Hatada, M. Kojima, M. Fukuda, Kazuo Sukegawa, Naoyoshi Tamura, Hiroshi Morioka, Kazuo Kawamura, T. Sakuma, J. Ogura, Y. S. Kim, Hiroyuki Ohta
Publikováno v:
2006 International Electron Devices Meeting.
The impact of defects on the short channel effects (SCE) and the drivability of a pMOSFET with a SiGe source/drain is described, and useful methods to reduce defect formation are suggested. The influence of defects on device performance is found to b
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae1a825555710c7ee3e6244c9548200b
https://doi.org/10.1109/iedm.2006.346920
https://doi.org/10.1109/iedm.2006.346920
Autor:
Shin'ichi Kawai, Hirokazu Suzuki, Suguru Warashina, Osamu Tsuboi, Kazuo Sukegawa, Keniji Takada, Seiichiro Kawamura, Shinichi Sekine
Publikováno v:
Japanese Journal of Applied Physics. 35:988
This paper describes the various advantages of silicon on insulator (SOI) circuits when well-established 0.8 µm Complementary Metal Oxide Semiconductor (CMOS) mass-production technologies for ultra-low power 1 V phase locked loop (PLL) circuits are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8b057364c7d23e8fc088a25460c0a8a7
https://doi.org/10.1143/jjap.35.988
https://doi.org/10.1143/jjap.35.988