Zobrazeno 1 - 10
of 36
pro vyhledávání: '"Kazuhito Higuchi"'
Autor:
Mitsuo SANO, Susumu OBATA, Takayuki TAJIMA, Yasunari UKITA, Kazuhito HIGUCHI, Ayumu MATSUMOTO, Shinji YAE
Publikováno v:
Journal of Smart Processing. 11:239-245
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af3cec3a4cb283ab56e83e31bda81efa
https://doi.org/10.7791/jspmee.11.239
https://doi.org/10.7791/jspmee.11.239
Publikováno v:
International Symposium on Microelectronics. 2019:000248-000253
In silicon capacitors, it is most important to increase the surface area of the surface forming the capacitor. In conventional silicon capacitors, trenches are generally formed in silicon wafer using reactive ion etching (RIE) method to expand their
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2a27e8264231807b5973d0c9f67bea9d
https://doi.org/10.4071/2380-4505-2019.1.000248
https://doi.org/10.4071/2380-4505-2019.1.000248
Autor:
Kazuhito Higuchi
Publikováno v:
Journal of The Japan Institute of Electronics Packaging. 23:543-543
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55a16a0fe890762670329a36037b6738
https://doi.org/10.5104/jiep.23.543
https://doi.org/10.5104/jiep.23.543
Autor:
Hisashi Ito, Tsuyoshi Sato, Matsuo Keiichiro, Kazuhito Higuchi, Yusaku Asano, Shimokawa Kazuo
Publikováno v:
2015 IEEE 65th Electronic Components and Technology Conference (ECTC).
A novel wafer dicing method that can singulate silicon wafers into individual dies at once has been developed. Since this method relies on chemical reactions, we call it Chemical Dicing. Chemical Dicing has the advantages of high throughput, narrow d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3f161b4910b2f3b90bd52467673f0869
https://doi.org/10.1109/ectc.2015.7159692
https://doi.org/10.1109/ectc.2015.7159692
Publikováno v:
Journal of Japan Institute of Electronics Packaging. 2:29-34
はんだ (鉛/スズ) に溶解ダメージを与えないニッケルエッチング液の設計を目的に, 三角図表示を用いて塩酸/硝酸/酢酸3成分系溶液におけるエッチング選択比の高い溶液混合比を求めた。
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5ffceef73b0894a01825c6d44755f8d8
https://doi.org/10.5104/jiep.2.29
https://doi.org/10.5104/jiep.2.29
Autor:
Hideki Shibata, Akihiro Kojima, Miyuki Shimojuku, Yoshiaki Sugizaki, Susumu Obata, Hideto Furuyama, Yosuke Akimoto, Miyoko Shimada, Kazuhito Higuchi
Publikováno v:
2012 IEEE International Interconnect Technology Conference.
Reduction of cost has become the most important challenge for solid state lighting. We proposed a novel Wafer-Level LED Packaging (WL2P) technology, which enables both extremely low cost and small size for future solid state lighting. Where a convent
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::76b93704478e21b24c21fdaec69a9f93
https://doi.org/10.1109/iitc.2012.6251634
https://doi.org/10.1109/iitc.2012.6251634
Autor:
Susumu Obata, Kazuhito Higuchi, Ryuichi Togawa, Miyuki Shimojuku, Akiya Kimura, Akihiro Kojima, Toshiya Nakayama, Yosuke Akimoto, Takayoshi Fujii, Hiroshi Koizumi
Publikováno v:
2012 IEEE 62nd Electronic Components and Technology Conference.
In this paper, we describe optical characteristics and reliability of a novel wafer level white LED (light-emitting diode) package. In this package, re-distribution wiring layer and phosphor layer could be formed in a lump by wafer level process. As
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d4ae1bccb165e1904ccb942dd4e1eb8d
https://doi.org/10.1109/ectc.2012.6249018
https://doi.org/10.1109/ectc.2012.6249018
Autor:
Mitsuyoshi Endo, Susumu Obata, Takeshi Miyagi, M. Nakao, I. Mori, Kazuhito Higuchi, Yoshiaki Sugizaki, Hideki Shibata, Akihiro Kojima, Yoshiaki Shimooka, Michinobu Inoue
Publikováno v:
2008 58th Electronic Components and Technology Conference.
Novel wafer-level chip scale package (WL-CSP) applicable to configurations involving stacking of multiple dies has been developed. Since stacked die makes high topography and it is difficult to apply conventional WL-CSP process, gold bonding wires we
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dc60fd5138dce2eb1eb588773700c568
https://doi.org/10.1109/ectc.2008.4550068
https://doi.org/10.1109/ectc.2008.4550068
Autor:
Hisashi Ito, Hideo Nishiuchi, Hirokazu Ezawa, Masayuki Uchida, K. Yabui, Takashi Togasaki, Kazuhito Higuchi
Publikováno v:
2007 Proceedings 57th Electronic Components and Technology Conference.
Flip chip bonding technology has been widely used for interconnection in high-end logic LSI employing lead-rich solder bumps. Recently, from an environmental issue, it is desired that the lead-rich solder should be replaced by lead-free solder. Howev
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::24a97fe1c59f3d224ed45d6fc252b64f
https://doi.org/10.1109/ectc.2007.373903
https://doi.org/10.1109/ectc.2007.373903
Publikováno v:
2006 1st Electronic Systemintegration Technology Conference.
Sn-Cu bumping has been demonstrated to employ sequential electroplating of Cu and Sn, followed by alloying the Cu/Sn stacks during reflow. Alloying behavior of the Cu/Sn stacks has been investigated with varying the underlying Cu thickness. The Cu6Sn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::95a268a2df5603b779e0650cc4fd7ce3
https://doi.org/10.1109/estc.2006.280057
https://doi.org/10.1109/estc.2006.280057